System and method for offsetting the data buffer latency of a device implementing a jedec standard ddr-4 lrdimm chipset

Abstract

A system and method for offsetting the data buffer latency in a CPIO device having a JEDEC standard DDR-4 LRDIMM chipset as the front end is disclosed. According to one embodiment, a CPIO ASIC provides variable timing control for its DDR-4 LRDIMM interface such that propagation delay of the data buffers can be offset by the CPIO ASIC, allowing the CPIO LRDIMM to be timing compatible with an RDIMM.

1 . A co-processing or input/output (CPIO) module with a load-reduction dual in-line memory module (LRDIMM) interface, the CPIO module comprising:
 a CPIO device;   a CPIO variable timing control circuit; and   a load-reduction dual in-line memory module (LRDIMM) interface configured to interface with a memory bus, the LRDIMM interface comprising data buffers to bridge data between the CPIO variable timing control circuit and the memory bus,   
       wherein the CPIO variable timing control circuit is operatively coupled between the LRDIMM interface and the CPIO device, and is configured to provide variable timing control to signaling between the CPIO variable timing control circuit and the LRDIMM interface.