Inventor · disambiguated record
Mukta G. Farooq
Also filed as: FAROOQ MUKTA · FAROOQ MUKTA G · FAROOQ MUKTA GHATE
223 granted patents·61 pending applications·2,247 citations·filing 2001–2024
99Inventor score
Top patents by PatentIndex Score
284 records- 0199US8916448B2Metal to metal bonding for stacked (3D) integrated circuitsIBM·Filed 2013·Granted Dec 23, 2014·82 cites·20 claims
- 0299US8841777B2Bonded structure employing metal semiconductor alloy bondingFAROOQ MUKTA G·Filed 2010·Granted Sep 23, 2014·216 cites·16 claims
- 0399US8563403B1Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation lastFAROOQ MUKTA G·Filed 2012·Granted Oct 22, 2013·184 cites·20 claims
- 0499US8158515B2Method of making 3D integrated circuitsFAROOQ MUKTA G·Filed 2010·Granted Apr 17, 2012·281 cites·14 claims
- 0599US8129256B23D integrated circuit device fabrication with precisely controllable substrate removalFAROOQ MUKTA G·Filed 2008·Granted Mar 6, 2012·254 cites·18 claims
- 0698US11984401B2Stacked FET integration with BSPDNIBM·Filed 2021·Granted May 14, 2024·5 cites·8 claims
- 0798US10215695B1Inspection system and method for detecting defects at a materials interfaceGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 26, 2019·15 cites·20 claims
- 0898US7955955B2Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structuresIBM·Filed 2007·Granted Jun 7, 2011·70 cites·22 claims
- 0997US12057371B2Semiconductor device with early buried power rail (BPR) and backside power distribution network (BSPDN)IBM·Filed 2021·Granted Aug 6, 2024·5 cites·12 claims
- 1095US8492878B2Metal-contamination-free through-substrate via structureFAROOQ MUKTA G·Filed 2010·Granted Jul 23, 2013·21 cites·24 claims
- 1195US8242604B2Coaxial through-silicon viaVOLANT RICHARD P·Filed 2009·Granted Aug 14, 2012·33 cites·13 claims
- 1295US7696631B2Wire bonding personalization and discrete component attachment on wirebond padsIBM·Filed 2007·Granted Apr 13, 2010·44 cites·20 claims
- 1395US7312529B2Structure and method for producing multiple size interconnectionsIBM·Filed 2005·Granted Dec 25, 2007·36 cites·18 claims
- 1494US8709936B2Method and structure of forming backside through silicon via connectionsVOLANT RICHARD P·Filed 2012·Granted Apr 29, 2014·15 cites·8 claims
- 1594US8076756B2Structure for inhibiting back end of line damage from dicing and chip packaging interaction failuresLANE MICHAEL W·Filed 2011·Granted Dec 13, 2011·21 cites·20 claims
- 1693US8394715B2Method of fabricating coaxial through-silicon viaVOLANT RICHARD P·Filed 2012·Granted Mar 12, 2013·16 cites·19 claims
- 1793US7348270B1Techniques for forming interconnectsIBM·Filed 2007·Granted Mar 25, 2008·23 cites·22 claims
- 1892US11973058B2Multiple die assemblyIBM·Filed 2021·Granted Apr 30, 2024·2 cites·20 claims
- 1992US10438894B1Chip-to-chip and chip-to-substrate interconnections in multi-chip semiconductor devicesGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 8, 2019·13 cites·20 claims
- 2092US9401323B1Protected through semiconductor via (TSV)IBM·Filed 2015·Granted Jul 26, 2016·8 cites·10 claims
- 2192US8791009B2Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon viaFAROOQ MUKTA G·Filed 2011·Granted Jul 29, 2014·11 cites·9 claims
- 2292US8748288B2Bonded structure with enhanced adhesion strengthFAROOQ MUKTA G·Filed 2010·Granted Jun 10, 2014·12 cites·12 claims
- 2392US8492241B2Method for simultaneously forming a through silicon via and a deep trench structureCHENG KANGGUO·Filed 2010·Granted Jul 23, 2013·12 cites·20 claims
- 2492US8120175B2Soft error rate mitigation by interconnect structureFAROOQ MUKTA G·Filed 2007·Granted Feb 21, 2012·23 cites·8 claims
- 2591US10068899B2IC structure on two sides of substrate and method of formingGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 4, 2018·8 cites·17 claims
- 2691US8674515B23D integrated circuits structureFAROOQ MUKTA G·Filed 2012·Granted Mar 18, 2014·11 cites·11 claims
- 2791US8017997B2Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact viaIBM·Filed 2008·Granted Sep 13, 2011·21 cites·12 claims
- 2891US7806341B2Structure for implementing secure multichip modules for encryption applicationsIBM·Filed 2009·Granted Oct 5, 2010·16 cites·26 claims
- 2991US7281667B2Method and structure for implementing secure multichip modules for encryption applicationsIBM·Filed 2005·Granted Oct 16, 2007·18 cites·4 claims
- 3090US10388567B2Thru-silicon-via structuresGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 20, 2019·6 cites·19 claims
- 3190US9059167B2Structure and method for making crack stop for 3D integrated circuitsIBM·Filed 2014·Granted Jun 16, 2015·8 cites·17 claims
- 3289US11404379B2Structure and method for bridge chip assembly with capillary underfillIBM·Filed 2020·Granted Aug 2, 2022·2 cites·20 claims
- 3389US10943883B1Planar wafer level fan-out of multi-chip modules having different size chipsIBM·Filed 2019·Granted Mar 9, 2021·6 cites·20 claims
- 3489US9812359B2Thru-silicon-via structuresIBM·Filed 2015·Granted Nov 7, 2017·6 cites·4 claims
- 3589US9406561B2Three dimensional integrated circuit integration using dielectric bonding first and through via formation lastFAROOQ MUKTA G·Filed 2009·Granted Aug 2, 2016·19 cites·27 claims
- 3689US8859390B2Structure and method for making crack stop for 3D integrated circuitsFAROOQ MUKTA G·Filed 2010·Granted Oct 14, 2014·9 cites·10 claims
- 3789US8822141B1Front side wafer ID processingIBM·Filed 2013·Granted Sep 2, 2014·10 cites·12 claims
- 3889US8487425B2Optimized annular copper TSVANDRY PAUL S·Filed 2011·Granted Jul 16, 2013·9 cites·15 claims
- 3989US8476168B2Non-conformal hardmask deposition for through silicon etchGRAVES-ABE TROY L·Filed 2011·Granted Jul 2, 2013·14 cites·16 claims
- 4088US8691691B2TSV pillar as an interconnecting structureFAROOQ MUKTA G·Filed 2011·Granted Apr 8, 2014·10 cites·16 claims
- 4187US11824037B2Assembly of a chip to a substrateIBM·Filed 2020·Granted Nov 21, 2023·2 cites·4 claims
- 4287US9806025B2SOI wafers with buried dielectric layers to prevent Cu diffusionGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 31, 2017·4 cites·10 claims
- 4387US8841200B2Simultaneously forming a through silicon via and a deep trench structureIBM·Filed 2013·Granted Sep 23, 2014·7 cites·13 claims
- 4487US8546961B2Alignment marks to enable 3D integrationFAROOQ MUKTA G·Filed 2011·Granted Oct 1, 2013·9 cites·19 claims
- 4587US8114707B2Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chipFAROOQ MUKTA G·Filed 2010·Granted Feb 14, 2012·8 cites·20 claims
- 4687US7079393B2Fluidic cooling systems and methods for electronic componentsIBM·Filed 2004·Granted Jul 18, 2006·44 cites·21 claims
- 4786US9891261B2Electromigration monitorIBM·Filed 2014·Granted Feb 13, 2018·6 cites·10 claims
- 4886US9330946B1Method and structure of die stacking using pre-applied underfillIBM·Filed 2015·Granted May 3, 2016·5 cites·21 claims
- 4986US8765597B2Fluorine depleted adhesion layer for metal interconnect structureIBM·Filed 2013·Granted Jul 1, 2014·5 cites·13 claims
- 5086US8492869B23D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layerFAROOQ MUKTA G·Filed 2012·Granted Jul 23, 2013·5 cites·20 claims
Showing the top 50 of 284 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →