Inventor · disambiguated record
Ngai Ngai William Hung
Also filed as: HUNG NGAI NGAI WILLIAM
17 granted patents·49 citations·filing 2009–2022
90Inventor score
Top patents by PatentIndex Score
17 records- 0192US11676068B1Method, product, and apparatus for a machine learning process leveraging input sparsity on a pixel by pixel basisCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Jun 13, 2023·4 cites·27 claims
- 0290US11651283B1Method, product, and apparatus for a machine learning process using dynamic rearrangement of sparse data and corresponding weightsCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted May 16, 2023·3 cites·24 claims
- 0390US11615320B1Method, product, and apparatus for variable precision weight management for neural networksCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Mar 28, 2023·3 cites·20 claims
- 0485US11687831B1Method, product, and apparatus for a multidimensional processing array for hardware acceleration of convolutional neural network inferenceCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Jun 27, 2023·2 cites·20 claims
- 0583US9202005B2Development and debug environment in a constrained random verificationSYNOPSYS INC·Filed 2014·Granted Dec 1, 2015·13 cites·19 claims
- 0680US8099690B2Adaptive state-to-symbolic transformation in a canonical representationGOSWAMI DHIRAJ·Filed 2009·Granted Jan 17, 2012·13 cites·20 claims
- 0779US9958917B1Generalized resettable memorySYNOPSYS INC·Filed 2016·Granted May 1, 2018·3 cites·20 claims
- 0877US11823018B1Method, product, and apparatus for a machine learning process using weight sharing within a systolic array having reduced memory bandwidthCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Nov 21, 2023·1 cites·20 claims
- 0970US11853668B1FPGA implementation interleaved with FPGA overlay architectures for emulationSYNOPSYS INC·Filed 2019·Granted Dec 26, 2023·1 cites·16 claims
- 1069US9720792B2Information theoretic caching for dynamic problem generation in constraint solvingGOSWAMI DHIRAJ·Filed 2012·Granted Aug 1, 2017·3 cites·36 claims
- 1163US10325046B2Formal method for clock tree analysis and optimizationSYNOPSYS INC·Filed 2017·Granted Jun 18, 2019·1 cites·20 claims
- 1262US8370273B2Method and apparatus for constructing a canonical representationSYNOPSYS INC·Filed 2009·Granted Feb 5, 2013·2 cites·20 claims
- 1349US10372856B2Optimizing constraint solving by rewriting at least one bit-slice constraintSYNOPSYS INC·Filed 2015·Granted Aug 6, 2019·0 cites·9 claims
- 1445US11868786B1Systems and methods for distributed and parallelized emulation processor configurationCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Jan 9, 2024·0 cites·18 claims
- 1544US11468218B2Information theoretic subgraph cachingSYNOPSYS INC·Filed 2013·Granted Oct 11, 2022·0 cites·26 claims
- 1643US9069699B2Identifying inconsistent constraintsGOSWAMI DHIRAJ·Filed 2011·Granted Jun 30, 2015·0 cites·21 claims
- 1740US9195634B2Optimizing constraint solving by rewriting at least one modulo constraintHUNG NGAI NGAI WILLIAM·Filed 2010·Granted Nov 24, 2015·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →