Inventor · disambiguated record
Oleg Levitsky
Also filed as: LEVITSKY OLEG
21 granted patents·1 pending application·367 citations·filing 1999–2014
96Inventor score
Technology areasG06F
Files withCADENCE DESIGN SYSTEMS INC8BHARDWAJ VIVEK4SYNOPSYS INC3ARORA SUMIT1CANDENCE DESGIN SYSTEMS INC1
Top patents by PatentIndex Score
22 records- 0196US8365113B1Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2010·Granted Jan 29, 2013·51 cites·31 claims
- 0294US8769455B1Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Jul 1, 2014·27 cites·35 claims
- 0393US8640066B1Multi-phase models for timing closure of integrated circuit designsGUPTA DINESH·Filed 2010·Granted Jan 28, 2014·34 cites·25 claims
- 0492US8572532B1Common path pessimism removal for hierarchical timing analysisSINGH SUSHOBHIT·Filed 2012·Granted Oct 29, 2013·42 cites·22 claims
- 0591US8935642B1Methods for single pass parallel hierarchical timing closure of integrated circuit designsBHARDWAJ VIVEK·Filed 2012·Granted Jan 13, 2015·13 cites·15 claims
- 0691US8539402B1Systems for single pass parallel hierarchical timing closure of integrated circuit designsBHARDWAJ VIVEK·Filed 2012·Granted Sep 17, 2013·13 cites·5 claims
- 0790US8977995B1Timing budgeting of nested partitions for hierarchical integrated circuit designsARORA SUMIT·Filed 2012·Granted Mar 10, 2015·36 cites·19 claims
- 0887US8504978B1User interface for timing budget analysis of integrated circuit designsBHARDWAJ VIVEK·Filed 2009·Granted Aug 6, 2013·23 cites·29 claims
- 0985US8719743B1Method and system for implementing clock tree prototypingCANDENCE DESGIN SYSTEMS INC·Filed 2012·Granted May 6, 2014·24 cites·37 claims
- 1085US7926011B1System and method of generating hierarchical block-level timing constraints from chip-level timing constraintsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Apr 12, 2011·16 cites·25 claims
- 1184US9165098B1Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Oct 20, 2015·5 cites·10 claims
- 1283US9152742B1Multi-phase models for timing closure of integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Oct 6, 2015·6 cites·21 claims
- 1383US8745560B1Methods for generating a user interface for timing budget analysis of integrated circuit designsBHARDWAJ VIVEK·Filed 2013·Granted Jun 3, 2014·8 cites·26 claims
- 1479US9141740B2Methods, systems, and articles of manufacture for implementing full-chip optimization with reduced physical design dataLIU DONGZI·Filed 2011·Granted Sep 22, 2015·9 cites·36 claims
- 1576US8151229B1System and method of computing pin criticalities under process variations for timing analysis and optimizationCHANG HONGLIANG·Filed 2007·Granted Apr 3, 2012·9 cites·23 claims
- 1672US9760667B1Method, system, and computer program product for implementing prototyping and floorplanning of electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Sep 12, 2017·3 cites·28 claims
- 1770US9053270B1Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jun 9, 2015·2 cites·20 claims
- 1870US8977994B1Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraintsLEVITSKY OLEG·Filed 2010·Granted Mar 10, 2015·4 cites·14 claims
- 1967US7930675B2Method and system for implementing timing analysis and optimization of an electronic design based upon extended regions of analysisCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Apr 19, 2011·4 cites·25 claims
- 2043US6378113B1Black box transparency in a circuit timing modelSYNOPSYS INC·Filed 1999·Granted Apr 23, 2002·20 cites·25 claims
- 2141US6704697B1Unified timing analysis for model interface layout parasiticsSYNOPSYS INC·Filed 1999·Granted Mar 9, 2004·18 cites·21 claims
- 2225US2004111247A1Optimization of timing models using bus compressionSYNOPSYS INC·Filed 1999·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Oleg Levitsky files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →