Inventor · disambiguated record
Patrick Morrow
Also filed as: MORROW PATRICK · MORROW PATRICK R · MORROW PATRICK S
189 granted patents·57 pending applications·2,017 citations·filing 1999–2025
99Inventor score
Top patents by PatentIndex Score
246 records- 0199US11239236B2Forksheet transistor architecturesINTEL CORP·Filed 2020·Granted Feb 1, 2022·9 cites·24 claims
- 0299US11201221B2Backside contact structures and fabrication for metal on both sides of devicesINTEL CORP·Filed 2020·Granted Dec 14, 2021·9 cites·24 claims
- 0399US7410884B23D integrated circuits using thick metal for backside connections and offset bumpsINTEL CORP·Filed 2005·Granted Aug 12, 2008·278 cites·25 claims
- 0498US11658221B2Backside contact structures and fabrication for metal on both sides of devicesINTEL CORP·Filed 2021·Granted May 23, 2023·3 cites·20 claims
- 0598US11616015B2Integrated circuit device with back-side interconnection to deep source/drain semiconductorINTEL CORP·Filed 2020·Granted Mar 28, 2023·3 cites·19 claims
- 0698US11594524B2Fabrication and use of through silicon vias on double sided interconnect deviceINTEL CORP·Filed 2022·Granted Feb 28, 2023·6 cites·20 claims
- 0798US7345479B2Portable NMR device and method for making and using the sameINTEL CORP·Filed 2005·Granted Mar 18, 2008·62 cites·53 claims
- 0898US7274191B2Integrated on-chip NMR and ESR device and method for making and using the sameINTEL CORP·Filed 2005·Granted Sep 25, 2007·62 cites·72 claims
- 0998US7056813B2Methods of forming backside connections on a wafer stackINTEL CORP·Filed 2005·Granted Jun 6, 2006·77 cites·51 claims
- 1098US6946384B2Stacked device underfill and a method of fabricationINTEL CORP·Filed 2003·Granted Sep 20, 2005·235 cites·23 claims
- 1197US10886217B2Integrated circuit device with back-side interconnection to deep source/drain semiconductorINTEL CORP·Filed 2016·Granted Jan 5, 2021·20 cites·20 claims
- 1297US10797139B2Methods of forming backside self-aligned vias and structures formed therebyINTEL CORP·Filed 2019·Granted Oct 6, 2020·22 cites·20 claims
- 1397US6797556B2MOS transistor structure and method of fabricationINTEL CORP·Filed 2003·Granted Sep 28, 2004·139 cites·21 claims
- 1496US11996411B2Stacked forksheet transistorsINTEL CORP·Filed 2020·Granted May 28, 2024·4 cites·21 claims
- 1596US11437283B2Backside contacts for semiconductor devicesINTEL CORP·Filed 2019·Granted Sep 6, 2022·12 cites·25 claims
- 1696US10872820B2Integrated circuit structuresINTEL CORP·Filed 2017·Granted Dec 22, 2020·22 cites·11 claims
- 1796US10304946B2Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devicesINTEL CORP·Filed 2015·Granted May 28, 2019·11 cites·21 claims
- 1896US7682916B2Field effect transistor structure with abrupt source/drain junctionsINTEL CORP·Filed 2008·Granted Mar 23, 2010·31 cites·10 claims
- 1996US7338873B2Method of fabricating a field effect transistor structure with abrupt source/drain junctionsINTEL CORP·Filed 2006·Granted Mar 4, 2008·28 cites·5 claims
- 2096US6897125B2Methods of forming backside connections on a wafer stackINTEL CORP·Filed 2003·Granted May 24, 2005·95 cites·17 claims
- 2196US6887762B1Method of fabricating a field effect transistor structure with abrupt source/drain junctionsINTEL CORP·Filed 1999·Granted May 3, 2005·141 cites·10 claims
- 2295US12176323B2Microelectronic assembliesINTEL CORP·Filed 2022·Granted Dec 24, 2024·2 cites·12 claims
- 2395US12107085B2Interconnect techniques for electrically connecting source/drain regions of stacked transistorsINTEL CORP·Filed 2023·Granted Oct 1, 2024·2 cites·20 claims
- 2495US10734412B2Backside contact resistance reduction for semiconductor devices with metallization on both sidesINTEL CORP·Filed 2016·Granted Aug 4, 2020·15 cites·20 claims
- 2595US9685436B2Monolithic three-dimensional (3D) ICs with local inter-level interconnectsINTEL CORP·Filed 2013·Granted Jun 20, 2017·24 cites·24 claims
- 2694US11664377B2Forksheet transistor architecturesINTEL CORP·Filed 2021·Granted May 30, 2023·2 cites·20 claims
- 2794US11342227B2Stacked transistor structures with asymmetrical terminal interconnectsINTEL CORP·Filed 2020·Granted May 24, 2022·3 cites·20 claims
- 2894US6479391B2Method for making a dual damascene interconnect using a multilayer hard maskINTEL CORP·Filed 2000·Granted Nov 12, 2002·88 cites·7 claims
- 2993US11264493B2Wrap-around source/drain method of making contacts for backside metalsINTEL CORP·Filed 2015·Granted Mar 1, 2022·9 cites·12 claims
- 3093US11139241B2Integrated circuit device with crenellated metal trace layoutINTEL CORP·Filed 2016·Granted Oct 5, 2021·6 cites·13 claims
- 3193US8421225B2Three-dimensional stacked substrate arrangementsRAMANATHAN SHRIRAM·Filed 2012·Granted Apr 16, 2013·14 cites·8 claims
- 3293US6541343B1Methods of making field effect transistor structure with partially isolated source/drain junctionsINTEL CORP·Filed 1999·Granted Apr 1, 2003·107 cites·21 claims
- 3392US10367070B2Methods of forming backside self-aligned vias and structures formed therebyINTEL CORP·Filed 2015·Granted Jul 30, 2019·8 cites·21 claims
- 3492US10297592B2Monolithic three-dimensional (3D) ICs with local inter-level interconnectsINTEL CORP·Filed 2017·Granted May 21, 2019·9 cites·16 claims
- 3591US11251156B2Fabrication and use of through silicon vias on double sided interconnect deviceINTEL CORP·Filed 2015·Granted Feb 15, 2022·8 cites·20 claims
- 3691US10490542B2Integrated circuit layout using library cells with alternating conductive linesINTEL CORP·Filed 2015·Granted Nov 26, 2019·8 cites·17 claims
- 3791US10068874B2Method for direct integration of memory die to logic die without use of thru silicon vias (TSV)INTEL CORP·Filed 2014·Granted Sep 4, 2018·15 cites·5 claims
- 3891US7436035B2Method of fabricating a field effect transistor structure with abrupt source/drain junctionsINTEL CORP·Filed 2004·Granted Oct 14, 2008·36 cites·7 claims
- 3990US11404319B2Vertically stacked finFETs and shared gate patterningINTEL CORP·Filed 2017·Granted Aug 2, 2022·5 cites·20 claims
- 4090US11094672B2Composite IC chips including a chiplet embedded within metallization layers of a host IC chipINTEL CORP·Filed 2019·Granted Aug 17, 2021·5 cites·20 claims
- 4190US10325840B2Metal on both sides with power distributed through the siliconINTEL CORP·Filed 2015·Granted Jun 18, 2019·6 cites·26 claims
- 4290US7129172B2Bonded wafer processing methodINTEL CORP·Filed 2004·Granted Oct 31, 2006·45 cites·22 claims
- 4389US12080605B2Backside contacts for semiconductor devicesINTEL CORP·Filed 2022·Granted Sep 3, 2024·1 cites·24 claims
- 4489US6448177B1Method of making a semiconductor device having a dual damascene interconnect spaced from a support structureINTEL CORP·Filed 2001·Granted Sep 10, 2002·56 cites·8 claims
- 4588US12288810B2Backside contact structures and fabrication for metal on both sides of devicesINTEL CORP·Filed 2024·Granted Apr 29, 2025·0 cites·20 claims
- 4688US11664373B2Isolation walls for vertically stacked transistor structuresINTEL CORP·Filed 2021·Granted May 30, 2023·1 cites·20 claims
- 4788US10396045B2Metal on both sides of the transistor integrated with magnetic inductorsINTEL CORP·Filed 2015·Granted Aug 27, 2019·6 cites·20 claims
- 4888US7755124B2Laminating magnetic materials in a semiconductor deviceINTEL CORP·Filed 2006·Granted Jul 13, 2010·18 cites·23 claims
- 4987US10784358B2Backside contact structures and fabrication for metal on both sides of devicesINTEL CORP·Filed 2015·Granted Sep 22, 2020·3 cites·4 claims
- 5087US7973407B2Three-dimensional stacked substrate arrangementsINTEL CORP·Filed 2008·Granted Jul 5, 2011·12 cites·12 claims
Showing the top 50 of 246 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →