Inventor · disambiguated record
Peter G. Tolchinsky
Also filed as: DATTA SUMAN · TOLCHINSKY PETER · TOLCHINSKY PETER G
28 granted patents·8 pending applications·727 citations·filing 2002–2016
97Inventor score
Top patents by PatentIndex Score
36 records- 0198US7569857B2Dual crystal orientation circuit devices on the same substrateINTEL CORP·Filed 2006·Granted Aug 4, 2009·119 cites·4 claims
- 0297US6908027B2Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening processINTEL CORP·Filed 2003·Granted Jun 21, 2005·224 cites·8 claims
- 0396US7491988B2Transistors with increased mobility in the channel zone and method of fabricationINTEL CORP·Filed 2004·Granted Feb 17, 2009·139 cites·28 claims
- 0495US7573059B2Dislocation-free InSb quantum well structure on Si using novel buffer architectureINTEL CORP·Filed 2006·Granted Aug 11, 2009·41 cites·17 claims
- 0593US7042009B2High mobility tri-gate devices and methods of fabricationINTEL CORP·Filed 2004·Granted May 9, 2006·80 cites·9 claims
- 0692US7494911B2Buffer layers for device isolation of devices grown on siliconINTEL CORP·Filed 2006·Granted Feb 24, 2009·19 cites·15 claims
- 0791US9691843B2Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or compositionINTEL CORP·Filed 2016·Granted Jun 27, 2017·7 cites·11 claims
- 0889US8143646B2Stacking fault and twin blocking barrier for integrating III-V on SiHUDAIT MANTU K·Filed 2006·Granted Mar 27, 2012·14 cites·16 claims
- 0988US10692839B2GaN devices on engineered silicon substratesINTEL CORP·Filed 2015·Granted Jun 23, 2020·5 cites·16 claims
- 1086US9559160B2Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or compositionCAPPELLANI ANNALISA·Filed 2011·Granted Jan 31, 2017·5 cites·15 claims
- 1185US8617945B2Stacking fault and twin blocking barrier for integrating III-V on SiHUDAIT MANTU K·Filed 2012·Granted Dec 31, 2013·6 cites·10 claims
- 1285US7161224B2Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening processINTEL CORP·Filed 2005·Granted Jan 9, 2007·12 cites·3 claims
- 1384US8217383B2High hole mobility p-channel Ge transistor structure on Si substrateHUDAIT MANTU K·Filed 2010·Granted Jul 10, 2012·5 cites·20 claims
- 1483US7687799B2Methods of forming buffer layer architecture on silicon and structures formed therebyINTEL CORP·Filed 2008·Granted Mar 30, 2010·8 cites·20 claims
- 1577US7791063B2High hole mobility p-channel Ge transistor structure on Si substrateINTEL CORP·Filed 2007·Granted Sep 7, 2010·4 cites·14 claims
- 1670US7863710B2Dislocation removal from a group III-V film grown on a semiconductor substrateINTEL CORP·Filed 2008·Granted Jan 4, 2011·3 cites·10 claims
- 1764US10600787B2Silicon PMOS with gallium nitride NMOS for voltage regulationINTEL CORP·Filed 2016·Granted Mar 24, 2020·1 cites·25 claims
- 1862US9711591B2Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed therebyMUKHERJEE NILOY·Filed 2011·Granted Jul 18, 2017·1 cites·10 claims
- 1960US7670928B2Ultra-thin oxide bonding for S1 to S1 dual orientation bondingINTEL CORP·Filed 2006·Granted Mar 2, 2010·1 cites·15 claims
- 2057US7851781B2Buffer layers for device isolation of devices grown on siliconINTEL CORP·Filed 2009·Granted Dec 14, 2010·0 cites·12 claims
- 2157US7473614B2Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layerINTEL CORP·Filed 2004·Granted Jan 6, 2009·6 cites·7 claims
- 2257US6911380B2Method of forming silicon on insulator wafersINTEL CORP·Filed 2002·Granted Jun 28, 2005·5 cites·21 claims
- 2354US6924543B2Method for making a semiconductor device having increased carrier mobilityINTEL CORP·Filed 2003·Granted Aug 2, 2005·6 cites·45 claims
- 2452US7091108B2Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devicesINTEL CORP·Filed 2003·Granted Aug 15, 2006·9 cites·7 claims
- 2551US2009096025A1Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layerTOLCHINSKY PETER G·Filed 2008·Application pending·0 cites
- 2649US7378331B2Methods of vertically stacking wafers using porous siliconINTEL CORP·Filed 2004·Granted May 27, 2008·5 cites·30 claims
- 2747US7531429B2Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devicesINTEL CORP·Filed 2006·Granted May 12, 2009·2 cites·13 claims
- 2846US2010155880A1Back gate doping for SOI substratesINTEL CORP·Filed 2008·Application pending·0 cites
- 2945US10879134B2Techniques for monolithic co-integration of silicon and III-N semiconductor transistorsINTEL CORP·Filed 2016·Granted Dec 29, 2020·0 cites·20 claims
- 3045US9691632B2Epitaxial wafer and a method of manufacturing thereofSILTRONIC AG·Filed 2013·Granted Jun 27, 2017·0 cites·20 claims
- 3144US2010148153A1Group III-V devices with delta-doped layer under channel regionHUDAIT MANTU K·Filed 2008·Application pending·0 cites
- 3243US2009071918A1Vertical semiconductor wafer carrierRAMANARAYANAN PANCHAPAKESAN·Filed 2007·Application pending·0 cites
- 3342US2007238281A1Depositing polar materials on non-polar semiconductor substratesHUDAIT MANTU K·Filed 2006·Application pending·0 cites
- 3440US2007063279A1Insulation layer for silicon-on-insulator waferTOLCHINSKY PETER G·Filed 2005·Application pending·0 cites
- 3539US2005217560A1Semiconductor wafers with non-standard crystal orientations and methods of manufacturing the sameTOLCHINSKY PETER G·Filed 2004·Application pending·0 cites
- 3637US2005070048A1Devices and methods employing high thermal conductivity heat dissipation substratesFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →