Inventor · disambiguated record
Praveen Kumar Verma
Also filed as: Verma Praveen Kumar
10 granted patents·6 pending applications·23 citations·filing 2015–2024
81Inventor score
Top patents by PatentIndex Score
16 records- 0187US12040013B2Static random access memory supporting a single clock cycle read-modify-write operationST MICROELECTRONICS INT NV·Filed 2022·Granted Jul 16, 2024·2 cites·35 claims
- 0282US9865333B2Temperature compensated read assist circuit for a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2016·Granted Jan 9, 2018·7 cites·22 claims
- 0370USD784247STire treadMICHELIN & CIE·Filed 2015·Granted Apr 18, 2017·14 cites·1 claims
- 0469US2025123758A1Modular memory architecture with more significant bit sub-array word line activation in single-cycle read-modify-write operation dependent on less significant bit sub-array data contentST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 0568US2025054529A1Sram with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applicationsST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 0662US12159689B2SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applicationsST MICROELECTRONICS INT NV·Filed 2022·Granted Dec 3, 2024·0 cites·19 claims
- 0761US12210754B2Modular memory architecture with more significant bit sub-array word line activation in single-cycle read-modify-write operation dependent on less significant bit sub-array data contentST MICROELECTRONICS INT NV·Filed 2022·Granted Jan 28, 2025·0 cites·21 claims
- 0856US12340099B2Static random access memory supporting a single clock cycle read-modify-write operation with a modulated word line assertionST MICROELECTRONICS INT NV·Filed 2023·Granted Jun 24, 2025·0 cites·21 claims
- 0951US2025054528A1Sram with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applicationsST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1049US2024331767A1Bit cell based write self-time delay pathST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1149US2024331768A1Bitcell process compensated read assist scheme for sramST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1247US2024363187A1Area saving high coverage fast diagnosis memory scan designST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1345US12068026B2Low power and fast memory resetST MICROELECTRONICS INT NV·Filed 2022·Granted Aug 20, 2024·0 cites·20 claims
- 1443US12046324B2Modular memory architecture with gated sub-array operation dependent on stored data contentST MICROELECTRONICS INT NV·Filed 2022·Granted Jul 23, 2024·0 cites·38 claims
- 1540US11594276B2Self-adjustable self-timed dual-rail SRAMSYNOPSYS INC·Filed 2020·Granted Feb 28, 2023·0 cites·30 claims
- 1637US11315630B2Parallel port enablement in pseudo-dual-port memory designsSYNOPSYS INC·Filed 2020·Granted Apr 26, 2022·0 cites·20 claims
Join the waitlist — get patent alerts
Get an alert when Praveen Kumar Verma files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →