Inventor · disambiguated record
R. Dean Adams
Also filed as: ADAMS R DEAN
16 granted patents·3 pending applications·1,001 citations·filing 1995–2004
95Inventor score
Top patents by PatentIndex Score
19 records- 0196US6163862AOn-chip test circuit for evaluating an on-chip signal using an external test signalIBM·Filed 1997·Granted Dec 19, 2000·459 cites·20 claims
- 0294US7168005B2Programable multi-port memory BIST with compact microcodeCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Jan 23, 2007·91 cites·41 claims
- 0392US6557127B1Method and apparatus for testing multi-port memoriesCADENCE DESIGN SYSTEMS INC·Filed 2000·Granted Apr 29, 2003·67 cites·18 claims
- 0490US6208572B1Semiconductor memory device having resistive bitline contact testingIBM·Filed 2000·Granted Mar 27, 2001·75 cites·20 claims
- 0587US6874111B1System initialization of microcode-based memory built-in self-testIBM·Filed 2000·Granted Mar 29, 2005·48 cites·15 claims
- 0686US5912901AMethod and built-in self-test apparatus for testing an integrated circuit which capture failure information for a selected failureIBM·Filed 1997·Granted Jun 15, 1999·85 cites·11 claims
- 0785US7203873B1Asynchronous control of memory self testMAGMA DESIGN AUTOMATION INC·Filed 2004·Granted Apr 10, 2007·46 cites·22 claims
- 0883US6651201B1Programmable memory built-in self-test combining microcode and finite state machine self-testIBM·Filed 2000·Granted Nov 18, 2003·36 cites·20 claims
- 0978US7308621B2Testing of ECC memoriesIBM·Filed 2002·Granted Dec 11, 2007·28 cites·19 claims
- 1072US7003704B2Two-dimensional redundancy calculationIBM·Filed 2002·Granted Feb 21, 2006·20 cites·13 claims
- 1160US6907554B2Built-in self test system and method for two-dimensional memory redundancy allocationIBM·Filed 2003·Granted Jun 14, 2005·11 cites·20 claims
- 1252US7149941B2Optimized ECC/redundancy fault recoveryIBM·Filed 2002·Granted Dec 12, 2006·3 cites·20 claims
- 1350US5592142AHigh speed greater than or equal to compare circuitIBM·Filed 1995·Granted Jan 7, 1997·24 cites·8 claims
- 1445US6681350B2Method and apparatus for testing memory cells for data retention faultsCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Jan 20, 2004·6 cites·11 claims
- 1538US7032144B2Method and apparatus for testing multi-port memoriesCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Apr 18, 2006·1 cites·12 claims
- 1631US2002116673A1Method and apparatus for testing memoryIBM·Filed 2000·Application pending·0 cites
- 1731US2002114202A1Method and apparatus for testing memoryIBM·Filed 2000·Application pending·0 cites
- 1830US6181155B1Method and apparatus for testing dynamic logic using an improved reset pulseIBM·Filed 1999·Granted Jan 30, 2001·1 cites·8 claims
- 1930US2005066226A1Redundant memory self-testFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →