Inventor · disambiguated record
Ralf Illgen
Also filed as: ILLGEN RALF
24 granted patents·11 pending applications·113 citations·filing 2009–2017
94Inventor score
Top patents by PatentIndex Score
35 records- 0195US9224840B2Replacement gate FinFET structures with high mobility channelFLACHOWSKY STEFAN·Filed 2012·Granted Dec 29, 2015·27 cites·12 claims
- 0292US9449972B1Ferroelectric FinFETGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 20, 2016·7 cites·16 claims
- 0390US8835936B2Source and drain doping using doped raised source and drain regionsGLOBALFOUNDRIES INC·Filed 2012·Granted Sep 16, 2014·11 cites·24 claims
- 0489US8912606B2Integrated circuits having protruding source and drain regions and methods for forming integrated circuitsBALDAUF TIM·Filed 2012·Granted Dec 16, 2014·16 cites·14 claims
- 0587US9899417B2Semiconductor structure including a first transistor and a second transistorGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 20, 2018·4 cites·20 claims
- 0687US9012277B2In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devicesFLACHOWSKY STEFAN·Filed 2012·Granted Apr 21, 2015·8 cites·27 claims
- 0783US8536034B2Methods of forming stressed silicon-carbon areas in an NMOS transistorFLACHOWSKY STEFAN·Filed 2011·Granted Sep 17, 2013·5 cites·20 claims
- 0882US9023713B2Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating sameILLGEN RALF·Filed 2012·Granted May 5, 2015·5 cites·17 claims
- 0979US8143133B2Technique for enhancing dopant profile and channel conductivity by millisecond anneal processesHOENTSCHEL JAN·Filed 2009·Granted Mar 27, 2012·5 cites·23 claims
- 1078US8338885B2Technique for enhancing dopant profile and channel conductivity by millisecond anneal processesHOENTSCHEL JAN·Filed 2012·Granted Dec 25, 2012·3 cites·14 claims
- 1176US8580643B2Threshold voltage adjustment in a Fin transistor by corner implantationBALDAUF TIM·Filed 2011·Granted Nov 12, 2013·4 cites·20 claims
- 1275US8835255B2Method of forming a semiconductor structure including a vertical nanowireGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 16, 2014·4 cites·20 claims
- 1372US10176859B2Non-volatile transistor element including a buried ferroelectric material based storage mechanismGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 8, 2019·4 cites·20 claims
- 1471US8753969B2Methods for fabricating MOS devices with stress memorizationFLACHOWSKY STEFAN·Filed 2012·Granted Jun 17, 2014·3 cites·7 claims
- 1570US10056376B2Ferroelectric FinFETGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 21, 2018·1 cites·19 claims
- 1669US9583240B2Temperature independent resistorGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 28, 2017·2 cites·13 claims
- 1767US8466018B2Methods of forming a PMOS device with in situ doped epitaxial source/drain regionsILLGEN RALF·Filed 2011·Granted Jun 18, 2013·3 cites·21 claims
- 1858US9269714B2Device including a transistor having a stressed channel region and method for the formation thereofGLOBALFOUNDRIES INC·Filed 2013·Granted Feb 23, 2016·1 cites·21 claims
- 1951US8916928B2Threshold voltage adjustment in a fin transistor by corner implantationGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 23, 2014·0 cites·17 claims
- 2048US9685457B2Method including a formation of a transistor and semiconductor structure including a first transistor and a second transistorGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 20, 2017·0 cites·18 claims
- 2146US2015214121A1Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating sameGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 2244US8647951B2Implantation of hydrogen to improve gate insulation layer-substrate interfaceFLACHOWSKY STEFAN·Filed 2011·Granted Feb 11, 2014·0 cites·15 claims
- 2343US9966466B2Semiconductor-on-insulator wafer, semiconductor structure including a transistor, and methods for the formation and operation thereofGLOBALFOUNDRIES INC·Filed 2016·Granted May 8, 2018·0 cites·26 claims
- 2442US8476131B2Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising sameFLACHOWSKY STEFAN·Filed 2011·Granted Jul 2, 2013·0 cites·15 claims
- 2542US2016071954A1Robust post-gate spacer processing and deviceGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 2641US2014246696A1Transistor with embedded strain-inducing material formed in cavities formed in a silicon/germanium substrateGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
- 2740US2013244437A1Methods of forming features on an integrated circuit product using a novel compound sidewall image transfer techniqueFLACHOWSKY STEFAN·Filed 2012·Application pending·0 cites
- 2840US2014117418A1Three-dimensional silicon-based transistor comprising a high-mobility channel formed by non-masked epitaxyGLOBALFOUNDRIES INC·Filed 2012·Application pending·0 cites
- 2939US2014030876A1Methods for fabricating high carrier mobility finfet structuresFLACHOWSKY STEFAN·Filed 2012·Application pending·0 cites
- 3038US2013032877A1N-channel transistor comprising a high-k metal gate electrode structure and a reduced series resistance by epitaxially formed semiconductor material in the drain and source areasGLOBALFOUNDRIES INC·Filed 2012·Application pending·0 cites
- 3137US8941187B2Strain engineering in three-dimensional transistors based on strained isolation materialBALDAUF TIM·Filed 2012·Granted Jan 27, 2015·0 cites·8 claims
- 3237US2017338350A1Semiconductor device and methodGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 3336US2013175640A1Stress enhanced mos transistor and methods for fabricationILLGEN RALF·Filed 2012·Application pending·0 cites
- 3436US2012231591A1Methods for fabricating cmos integrated circuits having metal silicide contactsFLACHOWSKY STEFAN·Filed 2011·Application pending·0 cites
- 3535US2013069123A1Cmos semiconductor devices having stressor regions and related fabrication methodsILLGEN RALF·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →