Inventor · disambiguated record
Rajarshi Mukherjee
Also filed as: MUKHERJEE RAJARSHI
25 granted patents·1 pending application·519 citations·filing 1995–2022
95Inventor score
Files withSYNOPSYS INC14FUJITSU LTD7APPLE INC1CADENCE DESIGN SYSTEMS INC1CALYPTO DESIGN SYSTEMS INC1
Top patents by PatentIndex Score
26 records- 0198US6301687B1Method for verification of combinational circuits using a filtering oriented approachFUJITSU LTD·Filed 2000·Granted Oct 9, 2001·135 cites·3 claims
- 0294US6086626AMethod for verification of combinational circuits using a filtering oriented approachFIJUTSU LIMITED·Filed 1997·Granted Jul 11, 2000·143 cites·52 claims
- 0393US11467851B1Machine learning (ML)-based static verification for derived hardware-design elementsSYNOPSYS INC·Filed 2020·Granted Oct 11, 2022·3 cites·20 claims
- 0487US7350168B1System, method and computer program product for equivalence checking between designs with sequential differencesCALYPTO DESIGN SYSTEMS INC·Filed 2005·Granted Mar 25, 2008·23 cites·26 claims
- 0584US10460059B1System and method for generating reduced standard delay format files for gate level simulationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Oct 29, 2019·8 cites·17 claims
- 0678US9529948B2Minimizing crossover paths for functional verification of a circuit descriptionSYNOPSYS INC·Filed 2014·Granted Dec 27, 2016·5 cites·30 claims
- 0778US5649165ATopology-based computer-aided design system for digital circuits and method thereofFUJITSU LTD·Filed 1995·Granted Jul 15, 1997·88 cites·62 claims
- 0875US6532440B1Multiple error and fault diagnosis based on XlistsFUJITSU LTD·Filed 1998·Granted Mar 11, 2003·39 cites·14 claims
- 0971US10831961B2Automated coverage convergence by correlating random variables with coverage variables sampled from simulation result dataSYNOPSYS INC·Filed 2019·Granted Nov 10, 2020·2 cites·20 claims
- 1071US9032339B2Ranking verification results for root cause analysisSYNOPSYS INC·Filed 2013·Granted May 12, 2015·3 cites·30 claims
- 1169US7194710B2Scheduling events in a boolean satisfiability (SAT) solverFUJITSU LTD·Filed 2004·Granted Mar 20, 2007·13 cites·22 claims
- 1269US6408424B1Verification of sequential circuits with same state encodingFUJITSU LTD·Filed 1999·Granted Jun 18, 2002·30 cites·40 claims
- 1368US7032192B2Performing latch mapping of sequential circuitsFUJITSU LTD·Filed 2003·Granted Apr 18, 2006·15 cites·34 claims
- 1463US9792394B2Accurate glitch detectionSYNOPSYS INC·Filed 2016·Granted Oct 17, 2017·1 cites·20 claims
- 1562US7383168B2Method and system for design verification and debugging of a complex computing systemFUJITSU LTD·Filed 2003·Granted Jun 3, 2008·11 cites·15 claims
- 1660US11288427B2Automated root-cause analysis, visualization, and debugging of static verification resultsSYNOPSYS INC·Filed 2020·Granted Mar 29, 2022·0 cites·20 claims
- 1755US11886877B1Memory select register to simplify operand mapping in subroutinesAPPLE INC·Filed 2021·Granted Jan 30, 2024·0 cites·20 claims
- 1852US12393754B2Generating a reduced block model view on-the-flySYNOPSYS INC·Filed 2022·Granted Aug 19, 2025·0 cites·19 claims
- 1952US10586001B2Automated root-cause analysis, visualization, and debugging of static verification resultsSYNOPSYS INC·Filed 2019·Granted Mar 10, 2020·0 cites·20 claims
- 2051US11403450B2Convergence centric coverage for clock domain crossing (CDC) jitter in simulationSYNOPSYS INC·Filed 2020·Granted Aug 2, 2022·0 cites·20 claims
- 2150US11907631B2Reset domain crossing detection and simulationSYNOPSYS INC·Filed 2021·Granted Feb 20, 2024·0 cites·19 claims
- 2250US11222154B2State table complexity reduction in a hierarchical verification flowSYNOPSYS INC·Filed 2020·Granted Jan 11, 2022·0 cites·20 claims
- 2345US9886753B2Verification of circuit structures including sub-structure variantsSYNOPSYS INC·Filed 2014·Granted Feb 6, 2018·0 cites·19 claims
- 2443US9069699B2Identifying inconsistent constraintsGOSWAMI DHIRAJ·Filed 2011·Granted Jun 30, 2015·0 cites·21 claims
- 2541US11556406B2Automatic root cause analysis of complex static violations by static information repository explorationSYNOPSYS INC·Filed 2019·Granted Jan 17, 2023·0 cites·20 claims
- 2641US2016180012A1Low Power Verification Method for a Circuit Description and System for Automating a Minimization of a Circuit DescriptionSYNOPSYS INC·Filed 2014·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →