Inventor · disambiguated record
Richard E. Schenker
Also filed as: SCHENKER RICHARD · SCHENKER RICHARD E · SCHENKER RICHARD ELLIOT
58 granted patents·25 pending applications·283 citations·filing 1998–2024
98Inventor score
Top patents by PatentIndex Score
83 records- 0196US11996411B2Stacked forksheet transistorsINTEL CORP·Filed 2020·Granted May 28, 2024·4 cites·21 claims
- 0296US11437283B2Backside contacts for semiconductor devicesINTEL CORP·Filed 2019·Granted Sep 6, 2022·12 cites·25 claims
- 0396US10892223B2Advanced lithography and self-assembled devicesINTEL CORP·Filed 2016·Granted Jan 12, 2021·11 cites·25 claims
- 0496US9793163B2Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnectsINTEL CORP·Filed 2013·Granted Oct 17, 2017·28 cites·11 claims
- 0595US12218052B2Advanced lithography and self-assembled devicesINTEL CORP·Filed 2023·Granted Feb 4, 2025·1 cites·20 claims
- 0694US9236342B2Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnectsBRISTOL ROBERT L·Filed 2013·Granted Jan 12, 2016·21 cites·20 claims
- 0793US10032643B2Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner schemeINTEL CORP·Filed 2014·Granted Jul 24, 2018·16 cites·25 claims
- 0891US11854787B2Advanced lithography and self-assembled devicesINTEL CORP·Filed 2022·Granted Dec 26, 2023·1 cites·19 claims
- 0991US10937689B2Self-aligned hard masks with converted linersINTEL CORP·Filed 2016·Granted Mar 2, 2021·7 cites·20 claims
- 1089US12080605B2Backside contacts for semiconductor devicesINTEL CORP·Filed 2022·Granted Sep 3, 2024·1 cites·24 claims
- 1188US2025125260A1Advanced lithography and self-assembled devicesINTEL CORP·Filed 2024·Application pending·0 cites
- 1285US11854882B2Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnectsTAHOE RES LTD·Filed 2020·Granted Dec 26, 2023·1 cites·25 claims
- 1385US11373950B2Advanced lithography and self-assembled devicesINTEL CORP·Filed 2020·Granted Jun 28, 2022·1 cites·19 claims
- 1485US6701004B1Detecting defects on photomasksINTEL CORP·Filed 1999·Granted Mar 2, 2004·67 cites·23 claims
- 1584US10553532B2Structure and method to self align via to top and bottom of tight pitch metal interconnect layersINTEL CORP·Filed 2014·Granted Feb 4, 2020·6 cites·25 claims
- 1684US2025029876A1Subtractive plug and tab patterning with photobuckets for back end of line (beol) spacer-based interconnectsTAHOE RES LTD·Filed 2024·Application pending·0 cites
- 1782US11011463B2Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication and structures resulting therefromINTEL CORP·Filed 2016·Granted May 18, 2021·3 cites·20 claims
- 1882US6883159B2Patterning semiconductor layers using phase shifting and assist featuresINTEL CORP·Filed 2002·Granted Apr 19, 2005·18 cites·18 claims
- 1981US11764263B2Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approachesINTEL CORP·Filed 2019·Granted Sep 19, 2023·2 cites·11 claims
- 2081US11569231B2Non-planar transistors with channel regions having varying widthsINTEL CORP·Filed 2019·Granted Jan 31, 2023·3 cites·21 claims
- 2181US9553018B2Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnectsINTEL CORP·Filed 2015·Granted Jan 24, 2017·3 cites·11 claims
- 2280US12506059B2Vertically spaced intra-level interconnect line metallization for integrated circuit devicesINTEL CORP·Filed 2024·Granted Dec 23, 2025·0 cites·20 claims
- 2380US2024213095A1Subtractive plug and tab patterning with photobuckets for back end of line (beol) spacer-based interconnectsTAHOE RES LTD·Filed 2023·Application pending·0 cites
- 2479US11239112B2Passivating silicide-based approaches for conductive via fabrication and structures resulting therefromINTEL CORP·Filed 2017·Granted Feb 1, 2022·3 cites·25 claims
- 2579US10109583B2Method for creating alternate hardmask cap interconnect structure with increased overlay marginINTEL CORP·Filed 2014·Granted Oct 23, 2018·4 cites·25 claims
- 2679US7816061B2Lithography masks for improved line-end patterningINTEL CORP·Filed 2007·Granted Oct 19, 2010·5 cites·15 claims
- 2778US7084960B2Lithography using controlled polarizationINTEL CORP·Filed 2004·Granted Aug 1, 2006·18 cites·29 claims
- 2877US9379010B2Methods for forming interconnect layers having tight pitch interconnect structuresINTEL CORP·Filed 2014·Granted Jun 28, 2016·4 cites·22 claims
- 2977US2024371700A1Backside contacts for semiconductor devicesINTEL CORP·Filed 2024·Application pending·0 cites
- 3076US2024038661A1Interconnects having a portion without a liner material and related structures, devices, and methodsINTEL CORP·Filed 2023·Application pending·0 cites
- 3175US2025046713A1Self-aligned patterning with colored blocking and structures resulting therefromINTEL CORP·Filed 2024·Application pending·0 cites
- 3274US11837542B2Interconnects having a portion without a liner material and related structures, devices, and methodsINTEL CORP·Filed 2022·Granted Dec 5, 2023·0 cites·25 claims
- 3374US11462469B2Single mask lithography line end enhancementINTEL CORP·Filed 2018·Granted Oct 4, 2022·2 cites·28 claims
- 3473US12080639B2Contact over active gate structures with metal oxide layers to inhibit shortingINTEL CORP·Filed 2019·Granted Sep 3, 2024·1 cites·17 claims
- 3573US2024234422A1Stacked forksheet transistorsINTEL CORP·Filed 2024·Application pending·0 cites
- 3672US12087836B2Contact over active gate structures with metal oxide-caped contacts to inhibit shortingINTEL CORP·Filed 2023·Granted Sep 10, 2024·0 cites·20 claims
- 3772US11972979B21D vertical edge blocking (VEB) via and plugINTEL CORP·Filed 2023·Granted Apr 30, 2024·0 cites·22 claims
- 3871US10867853B2Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnectsINTEL CORP·Filed 2016·Granted Dec 15, 2020·1 cites·23 claims
- 3970US10804141B2Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnectsINTEL CORP·Filed 2016·Granted Oct 13, 2020·1 cites·20 claims
- 4070US2023369399A1Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approachesINTEL CORP·Filed 2023·Application pending·0 cites
- 4169US9659860B2Method and structure to contact tight pitch conductive layers with guided viasINTEL CORP·Filed 2013·Granted May 23, 2017·2 cites·20 claims
- 4269US9312204B2Methods of forming parallel wires of different metal materials through double patterning and fill techniquesINTEL CORP·Filed 2013·Granted Apr 12, 2016·3 cites·26 claims
- 4368US10546772B2Self-aligned via below subtractively patterned interconnectINTEL CORP·Filed 2016·Granted Jan 28, 2020·1 cites·20 claims
- 4467US12012473B2Directed self-assembly structures and techniquesINTEL CORP·Filed 2020·Granted Jun 18, 2024·0 cites·20 claims
- 4566US11990403B2Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication and structures resulting therefromINTEL CORP·Filed 2021·Granted May 21, 2024·0 cites·6 claims
- 4665US11948874B2Vertically spaced intra-level interconnect line metallization for integrated circuit devicesINTEL CORP·Filed 2020·Granted Apr 2, 2024·0 cites·13 claims
- 4762US11373900B2Damascene plug and tab patterning with photobucketsINTEL CORP·Filed 2020·Granted Jun 28, 2022·0 cites·24 claims
- 4861US12087594B2Colored gratings in microelectronic structuresINTEL CORP·Filed 2020·Granted Sep 10, 2024·0 cites·20 claims
- 4959US2025301708A1Forksheet transistors with self-aligned dielectric spineINTEL CORP·Filed 2024·Application pending·0 cites
- 5058US12154855B2Self-aligned patterning with colored blocking and structures resulting therefromINTEL CORP·Filed 2019·Granted Nov 26, 2024·0 cites·16 claims
Showing the top 50 of 83 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →