Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches

Abstract

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.

What is claimed is: 
     
         1 . An integrated circuit structure, comprising:
 a first vertical arrangement of nanowires and a second vertical arrangement of nanowires, the first vertical arrangement of nanowires having an active uppermost nanowire and an oxide bottommost nanowire, the second vertical arrangement of nanowires having an oxide uppermost nanowire and an active bottommost nanowire, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires and co-planar bottommost nanowires;   a first gate structure over the first vertical arrangement of nanowires; and   a second gate structure over the second vertical arrangement of nanowires and around the oxide bottommost nanowire.   
     
     
         2 . The integrated circuit structure of  claim 1 , wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width the same as a horizontal width of the nanowires of the second vertical arrangement of nanowires. 
     
     
         3 . The integrated circuit structure of  claim 1 , wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width greater than a horizontal width of the nanowires of the second vertical arrangement of nanowires. 
     
     
         4 . The integrated circuit structure of  claim 1 , wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width less than a horizontal width of the nanowires of the second vertical arrangement of nanowires. 
     
     
         5 . The integrated circuit structure of  claim 1 , further comprising:
 first epitaxial source or drain structures at ends of the first vertical arrangement of nanowires; and   second epitaxial source or drain structures at ends of the second vertical arrangement of nanowires.   
     
     
         6 . The integrated circuit structure of  claim 5 , wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures. 
     
     
         7 . The integrated circuit structure of  claim 5 , wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures. 
     
     
         8 . The integrated circuit structure of  claim 5 , wherein the first gate structure has dielectric sidewall spacers, and the first epitaxial source or drain structures are first embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the first gate structure, and wherein the second gate structure has dielectric sidewall spacers, and the second epitaxial source or drain structures are second embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the second gate structure. 
     
     
         9 . The integrated circuit structure of  claim 5 , further comprising:
 a first pair of conductive contact structures coupled to the first epitaxial source or drain structures; and   a second pair of conductive contact structures coupled to the second epitaxial source or drain structures.   
     
     
         10 . The integrated circuit structure of  claim 1 , wherein the first vertical arrangement of nanowires is over a first fin, and the second vertical arrangement of nanowires is over a second fin. 
     
     
         11 . The integrated circuit structure of  claim 1 , further comprising:
 a gate endcap isolation structure between and in contact with the first gate structure and the second gate structure.   
     
     
         12 . An integrated circuit structure, comprising:
 a vertical arrangement of nanowires, wherein all nanowires of the vertical arrangement of nanowires are oxide nanowires;   a gate stack over the vertical arrangement of nanowires, around each of the oxide nanowires, wherein the gate stack comprises a conductive gate electrode.   
     
     
         13 . The integrated circuit structure of  claim 12 , further comprising:
 a gate contact above the vertical arrangement of nanowires, the gate contact in contact with a top surface of the conductive gate electrode; and   an interconnect structure below the vertical arrangement of nanowires, wherein a conductive via of the interconnect structure is in contact with a bottom surface of the conductive gate electrode, wherein the conductive gate electrode acts as a conductive via between the gate contact and the interconnect structures.   
     
     
         14 . The integrated circuit structure of  claim 12 , wherein the oxide nanowires of the vertical arrangement of nanowires have an oxidation catalyst layer thereon. 
     
     
         15 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including an integrated circuit structure, comprising: 
 a first vertical arrangement of nanowires and a second vertical arrangement of nanowires, the first vertical arrangement of nanowires having an active uppermost nanowire and an oxide bottommost nanowire, the second vertical arrangement of nanowires having an oxide uppermost nanowire and an active bottommost nanowire, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires and co-planar bottommost nanowires; 
 a first gate structure over the first vertical arrangement of nanowires; and 
 a second gate structure over the second vertical arrangement of nanowires and around the oxide bottommost nanowire. 
   
     
     
         16 . The computing device of  claim 15 , further comprising:
 a memory coupled to the board.   
     
     
         17 . The computing device of  claim 15 , further comprising:
 a communication chip coupled to the board.   
     
     
         18 . The computing device of  claim 15 , wherein the component is a packaged integrated circuit die. 
     
     
         19 . The computing device of  claim 15 , further comprising:
 a battery coupled to the board.   
     
     
         20 . The computing device of  claim 15 , further comprising:
 a display coupled to the board.