Interconnects having a portion without a liner material and related structures, devices, and methods

Abstract

Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.

1 . An integrated circuit structure, comprising:
 a conductive interconnect over a dielectric layer, the conductive interconnect having a bottom and sidewalls;   a conductive liner along the bottom and along lower portions of the sidewalls of the conductive interconnect, wherein the conductive liner has an uppermost surface; and   a dielectric liner laterally adjacent to the conductive liner, the dielectric liner over the dielectric layer, and the dielectric liner having an uppermost surface at a same level as the uppermost surface of the conductive liner.   
     
     
         2 . The integrated circuit structure of  claim 1 , wherein the bottom surface of the conductive interconnect is below an uppermost surface of the dielectric layer. 
     
     
         3 . The integrated circuit structure of  claim 1 , further comprising:
 an air gap laterally adjacent to the conductive interconnect, the air gap over the dielectric liner.   
     
     
         4 . The integrated circuit structure of  claim 1 , wherein the conductive interconnect comprises a metal selected from the group consisting of copper, cobalt, ruthenium, and aluminum. 
     
     
         5 . The integrated circuit structure of  claim 1 , wherein the conductive liner comprises a material selected from the group consisting of titanium nitride, titanium, ruthenium, tantalum nitride, and molybdenum nitride. 
     
     
         6 . The integrated circuit structure of  claim 1 , wherein the dielectric liner comprises a material selected from the group consisting of hafnium oxide, aluminum oxide, and carbon-doped silicon nitride. 
     
     
         7 . The integrated circuit structure of  claim 1 , further comprising:
 a second dielectric layer on the dielectric liner.   
     
     
         8 . A method of fabricating an integrated circuit structure, the method comprising:
 forming a conductive interconnect over a dielectric layer, the conductive interconnect having a bottom and sidewalls;   forming a conductive liner along the bottom and along lower portions of the sidewalls of the conductive interconnect, wherein the conductive liner has an uppermost surface; and   forming a dielectric liner laterally adjacent to the conductive liner, the dielectric liner over the dielectric layer, and the dielectric liner having an uppermost surface at a same level as the uppermost surface of the conductive liner.   
     
     
         9 . The method of  claim 8 , wherein the bottom surface of the conductive interconnect is below an uppermost surface of the dielectric layer. 
     
     
         10 . The method of  claim 8 , further comprising:
 forming an air gap laterally adjacent to the conductive interconnect, the air gap over the dielectric liner.   
     
     
         11 . The method of  claim 8 , wherein the conductive interconnect comprises a metal selected from the group consisting of copper, cobalt, ruthenium, and aluminum. 
     
     
         12 . The method of  claim 8 , wherein the conductive liner comprises a material selected from the group consisting of titanium nitride, titanium, ruthenium, tantalum nitride, and molybdenum nitride. 
     
     
         13 . The method of  claim 8 , wherein the dielectric liner comprises a material selected from the group consisting of hafnium oxide, aluminum oxide, and carbon-doped silicon nitride. 
     
     
         14 . The method of  claim 8 , further comprising:
 forming a second dielectric layer on the dielectric liner.   
     
     
         15 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including an integrated circuit structure, comprising:
 a conductive interconnect over a dielectric layer, the conductive interconnect having a bottom and sidewalls; 
 a conductive liner along the bottom and along lower portions of the sidewalls of the conductive interconnect, wherein the conductive liner has an uppermost surface; and 
 a dielectric liner laterally adjacent to the conductive liner, the dielectric liner over the dielectric layer, and the dielectric liner having an uppermost surface at a same level as the uppermost surface of the conductive liner. 
   
     
     
         16 . The computing device of  claim 15 , further comprising:
 a memory coupled to the board.   
     
     
         17 . The computing device of  claim 15 , further comprising:
 a communication chip coupled to the board.   
     
     
         18 . The computing device of  claim 15 , further comprising:
 a display coupled to the board.   
     
     
         19 . The computing device of  claim 15 , wherein the component is a packaged integrated circuit die. 
     
     
         20 . The computing device of  claim 15 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.