Inventor · disambiguated record
Rohit Kapur
Also filed as: KAPUR ROHIT
42 granted patents·2 pending applications·742 citations·filing 1996–2019
98Inventor score
Top patents by PatentIndex Score
44 records- 0196US7900105B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2010·Granted Mar 1, 2011·15 cites·35 claims
- 0294US6993694B1Deterministic bist architecture including MISR filterSYNOPSYS INC·Filed 2002·Granted Jan 31, 2006·75 cites·12 claims
- 0393US6807646B1System and method for time slicing deterministic patterns for reseeding in logic built-in self-testSYNOPSYS INC·Filed 2002·Granted Oct 19, 2004·61 cites·26 claims
- 0492US6385750B1Method and system for controlling test data volume in deterministic test pattern generationSYNOPSYS INC·Filed 1999·Granted May 7, 2002·97 cites·30 claims
- 0590US7418640B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2004·Granted Aug 26, 2008·28 cites·7 claims
- 0689US6766501B1System and method for high-level test planning for layoutSYNOPSYS INC·Filed 2002·Granted Jul 20, 2004·34 cites·26 claims
- 0787US8065651B2Implementing hierarchical design-for-test logic for modular circuit designKAPUR ROHIT·Filed 2009·Granted Nov 22, 2011·24 cites·21 claims
- 0887US6990619B1System and method for automatically retargeting test vectors between different tester typesSYNOPSYS INC·Filed 2001·Granted Jan 24, 2006·38 cites·29 claims
- 0986US8479067B2Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitryCHANDRA ANSHUMAN·Filed 2010·Granted Jul 2, 2013·12 cites·25 claims
- 1086US7797601B2Slack-based transition-fault testingSYNOPSYS INC·Filed 2009·Granted Sep 14, 2010·16 cites·16 claims
- 1186US7774663B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2009·Granted Aug 10, 2010·8 cites·7 claims
- 1285US7596733B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2008·Granted Sep 29, 2009·8 cites·7 claims
- 1384US7836367B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2009·Granted Nov 16, 2010·7 cites·56 claims
- 1483US7814444B2Scan compression circuit and method of design thereforSYNOPSYS INC·Filed 2007·Granted Oct 12, 2010·16 cites·17 claims
- 1581US9342439B2Command coverage analyzerSYNOPSYS INC·Filed 2015·Granted May 17, 2016·4 cites·20 claims
- 1681US7546500B2Slack-based transition-fault testingSYNOPSYS INC·Filed 2006·Granted Jun 9, 2009·12 cites·19 claims
- 1780US6615380B1Dynamic scan chains and test pattern generation methodologies thereforSYNOPSYS INC·Filed 1999·Granted Sep 2, 2003·91 cites·21 claims
- 1880US6434733B1System and method for high-level test planning for layoutSYNOPSYS INC·Filed 1999·Granted Aug 13, 2002·39 cites·26 claims
- 1979US6405355B1Method for placement-based scan-in and scan-out ports selectionSYNOPSYS INC·Filed 1999·Granted Jun 11, 2002·43 cites·22 claims
- 2077US7669098B2Method and apparatus for limiting power dissipation in testSYNOPSYS INC·Filed 2006·Granted Feb 23, 2010·8 cites·20 claims
- 2171US7836368B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2009·Granted Nov 16, 2010·3 cites·28 claims
- 2270US8584073B2Test design optimizer for configurable scan architecturesKAPUR ROHIT·Filed 2008·Granted Nov 12, 2013·7 cites·41 claims
- 2368US8954918B2Test design optimizer for configurable scan architecturesSYNOPSYS INC·Filed 2013·Granted Feb 10, 2015·2 cites·24 claims
- 2467US10605863B2Mapping physical shift failures to scan cells for detecting physical faults in integrated circuitsSYNOPSYS INC·Filed 2017·Granted Mar 31, 2020·1 cites·20 claims
- 2565US7743299B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2008·Granted Jun 22, 2010·2 cites·5 claims
- 2663US9568550B1Identifying failure indicating scan test cells of a circuit-under-testSYNOPSYS INC·Filed 2015·Granted Feb 14, 2017·1 cites·24 claims
- 2762US6631344B1Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generationSYNOPSYS INC·Filed 1999·Granted Oct 7, 2003·41 cites·13 claims
- 2861US9239897B2Hierarchical testing architecture using core circuit with pseudo-interfacesSYNOPSYS INC·Filed 2014·Granted Jan 19, 2016·1 cites·19 claims
- 2960US11237210B1Layout-aware test pattern generation and fault detectionSYNOPSYS INC·Filed 2019·Granted Feb 1, 2022·0 cites·15 claims
- 3058US6453437B1Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generationSYNOPSYS INC·Filed 1999·Granted Sep 17, 2002·32 cites·15 claims
- 3157US10203370B2Scheme for masking output of scan chains in test circuitSYNOPSYS INC·Filed 2017·Granted Feb 12, 2019·0 cites·15 claims
- 3257US8521464B2Accelerating automatic test pattern generation in a multi-core computing environment via speculatively scheduled sequential multi-level parameter value optimizationKUMAR ASHWIN·Filed 2010·Granted Aug 27, 2013·1 cites·20 claims
- 3356US9588179B2Scheme for masking output of scan chains in test circuitSYNOPSYS INC·Filed 2014·Granted Mar 7, 2017·0 cites·20 claims
- 3455US8660818B2Systemic diagnostics for increasing wafer yieldKAPUR ROHIT·Filed 2010·Granted Feb 25, 2014·2 cites·14 claims
- 3553US9417287B2Scheme for masking output of scan chains in test circuitSYNOPSYS INC·Filed 2014·Granted Aug 16, 2016·0 cites·20 claims
- 3653US2016341795A1Scheme for Masking Output of Scan Chains in Test CircuitSYNOPSYS INC·Filed 2016·Application pending·0 cites
- 3750US10445225B2Command coverage analyzerSYNOPSYS INC·Filed 2016·Granted Oct 15, 2019·0 cites·13 claims
- 3848US10067187B2Handling of undesirable distribution of unknown values in testing of circuit using automated test equipmentSYNOPSYS INC·Filed 2014·Granted Sep 4, 2018·0 cites·19 claims
- 3947US10621298B2Automatically generated schematics and visualizationSYNOPSYS INC·Filed 2016·Granted Apr 14, 2020·0 cites·20 claims
- 4046US5691990AHybrid partial scan methodIBM·Filed 1996·Granted Nov 25, 1997·13 cites·13 claims
- 4145US10254343B2Layout-aware test pattern generation and fault detectionSANYAL ALODEEP·Filed 2012·Granted Apr 9, 2019·0 cites·9 claims
- 4245US9411014B2Reordering or removal of test patterns for detecting faults in integrated circuitSYNOPSYS INC·Filed 2014·Granted Aug 9, 2016·0 cites·20 claims
- 4344US9329235B2Localizing fault flop in circuit by using modified test patternSYNOPSYS INC·Filed 2014·Granted May 3, 2016·0 cites·17 claims
- 4432US2002093356A1Intelligent test vector formatting to reduce test vector size and allow encryption thereof for integrated circuit testingFiled 2000·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →