Inventor · disambiguated record
Roy Knechtel
Also filed as: KNECHTEL ROY
7 granted patents·7 pending applications·11 citations·filing 2004–2020
76Inventor score
Files withX FAB SEMICONDUCTOR FOUNDRIES6X FAB SEMICONDUCTOR FOUNDRIES GMBH5KNECHTEL ROY2BUETTNER SIEGFRIED1
Top patents by PatentIndex Score
14 records- 0161US7509875B2Electrical determination of the connection quality of a bonded wafer connectionX FAB SEMICONDUCTOR FOUNDRIES·Filed 2006·Granted Mar 31, 2009·2 cites·22 claims
- 0260US10199274B2Electrically conductive via(s) in a semiconductor substrate and associated production methodX FAB SEMICONDUCTOR FOUNDRIES GMBH·Filed 2017·Granted Feb 5, 2019·1 cites·29 claims
- 0354US7790569B2Production of semiconductor substrates with buried layers by joining (bonding) semiconductor wafersX FAB SEMICONDUCTOR FOUNDRIES·Filed 2004·Granted Sep 7, 2010·7 cites·27 claims
- 0453US8021906B2Hermetic sealing and electrical contacting of a microelectromechanical structure, and microsystem (MEMS) produced therewithX FAB SEMICONDUCTOR FOUNDRIES·Filed 2007·Granted Sep 20, 2011·1 cites·33 claims
- 0549US2020258863A1Anodic Bonding of a Substrate of Glass having Contact Vias to a Substrate of SiliconX-FAB SEMICONDUCTOR FOUNDRIES GMBH·Filed 2020·Application pending·0 cites
- 0649US2020258862A1Anodic Bonding of a Substrate of Glass having Contact Vias to a Substrate of SiliconX-FAB SEMICONDUCTOR FOUNDRIES GMBH·Filed 2020·Application pending·0 cites
- 0748US11398452B2Anodic bonding of a substrate of glass having contact vias to a substrate of siliconX FAB SEMICONDUCTOR FOUNDRIES GMBH·Filed 2019·Granted Jul 26, 2022·0 cites·37 claims
- 0846US10825728B2Electrically conductive via(s) in a semiconductor substrate and associated production methodX FAB SEMICONDUCTOR FOUNDRIES GMBH·Filed 2018·Granted Nov 3, 2020·0 cites·20 claims
- 0943US2010330506A1Method for transferring an epitaxial layer from a donor wafer to a system wafer appertaining to microsystems technologyX FAB SEMICONDUCTOR FOUNDRIES·Filed 2008·Application pending·0 cites
- 1041US2010311248A1Structured layer deposition on processed wafers used in microsystem technologyX FAB SEMICONDUCTOR FOUNDRIES·Filed 2008·Application pending·0 cites
- 1141US2010282165A1Production of adjustment structures for a structured layer deposition on a microsystem technology waferX FAB SEMICONDUCTOR FOUNDRIES·Filed 2008·Application pending·0 cites
- 1226US8129255B2Firm, insulating and electrically conducting connection of processed semiconductor wafersKNECHTEL ROY·Filed 2004·Granted Mar 6, 2012·0 cites·11 claims
- 1325US2007031989A1Separating semiconductor wafers having exposed micromechanical structures into individual chipsKNECHTEL ROY·Filed 2004·Application pending·0 cites
- 1424US2006124915A1Production of an optoelectronic component that is enclosed in plastic, and corresponding methodsBUETTNER SIEGFRIED·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →