Anodic Bonding of a Substrate of Glass having Contact Vias to a Substrate of Silicon

Abstract

A semiconductor device comprising a first substrate ( 100 ) including silicon may include a bondable passivation ( 200 ) made of a bondable material, especially a glass material; at least one contact via ( 210 ) extending through the passivation and contacting a region of the first substrate ( 100 ); an interface ( 204 ) created by anodic bonding between the substrate including silicon and the bondable passivation ( 200 ), wherein silicon-oxygen-silicon bonds are formed in the interface in order to provide adhesion between the passivation ( 200 ) and the substrate ( 100 )

1 - 82 . (canceled) 
     
     
         83 . A semiconductor device comprising a first substrate ( 100 ) including silicon, and comprising:
 a bondable passivation ( 200 ) made of a bondable material, especially a glass material;   at least one contact via ( 210 ) extending through the passivation and contacting a region of the first substrate ( 100 );   an interface ( 204 ) created by anodic bonding between the substrate including silicon and the bondable passivation ( 200 ), wherein silicon-oxygen-silicon bonds are formed in the interface in order to provide adhesion between the passivation ( 200 ) and the substrate ( 100 ).   
     
     
         84 . The semiconductor device according to  claim 83 , wherein the bondable material of the passivation is a glass material. 
     
     
         85 . The semiconductor device according to  claim 83 , wherein the bondable passivation material ( 200 ) is an alkaline glass material having an adapted thermal expansion coefficient, or is a glass material, or is a glass-like material. 
     
     
         86 . The semiconductor device according to  claim 83 , wherein the bondable passivation material becomes sufficiently conductive under the influence of a temperature within a range of 300° C. to 500° C., thereby enabling ion migration and thus a current flow through the passivation material. 
     
     
         87 . The semiconductor device according to  claim 83 , wherein an upper electrode ( 3 ) or an electrode wafer ( 300 ) having recesses therein is provided, wherein the recesses are arranged above the through vias ( 210 ) of the passivation ( 200 ). 
     
     
         88 . The semiconductor device according to  claim 87 , wherein, for enabling a bonding process, the upper electrode ( 3 ) or the electrode wafer ( 300 ) does not contact the through vias ( 210 ) so that no short circuit occurs. 
     
     
         89 . The semiconductor device according to  claim 88 , wherein contacting the semiconductor wafer ( 100 ) is achieved:
 either via a lower bottom plate ( 2 ),   or by an edge pin ( 5 ) via recesses in the electrode wafer ( 300 ) and the passivation ( 200 ) accommodating the same.   
     
     
         90 . The semiconductor device according to  claim 83 , wherein the lower semiconductor wafer ( 100 ) can be contacted by the lower bottom plate ( 2 ) or the edge pin ( 5 ), especially when the edge pin ( 5 ) reaches through a recess in an electrode wafer ( 300 ). 
     
     
         91 . The semiconductor device according to  claim 90 , wherein the contacting is achieved when the edge pin ( 5 ) reaches through the recess in the electrode wafer ( 300 ). 
     
     
         92 . The semiconductor device according to  claim 83 , wherein an electrode wafer ( 300 ) is provided that comprises insulating fences in order to separate potentials for contacting the passivation ( 200 ) and for contacting the lower semiconductor wafer ( 100 ) via the through via ( 210 ). 
     
     
         93 . The semiconductor device according to  claim 92 , wherein the fences are realized by a glass-silicon-composite wafer including a high-resistance glass. 
     
     
         94 . The semiconductor device according to  claim 93 , wherein the electric contacting of the electrode wafer is achieved via a structured metal layer on the wafer backside. 
     
     
         95 . The semiconductor device according to  claim 94 , wherein the electric contacting of the electrode wafer is achieved via the structured metal layer on the wafer backside and is separated from other portions of the wafer having a structured electric insulating layer or a high-resistance barrier layer in order to prevent a current flow. 
     
     
         96 . The semiconductor device according to  claim 95 , wherein the preventing of a current flow is preventing a short circuit. 
     
     
         97 . The semiconductor device according to  claim 83 , wherein a metal layer on the passivation ( 200 ) is structured such that there is no metal in the position(s) of the contact via(s) ( 210 ). 
     
     
         98 . The semiconductor device according to  claim 83 , wherein the structured metal layer is located on the passivation ( 200 ) formed as a glass substrate. 
     
     
         99 . The semiconductor device according to  claim 97 , wherein the metal layer can be contacted by a center pin, and the first substrate ( 100 ) can be contacted via the lower bottom plate ( 2 ), or by the edge pin ( 5 ) via a recess in the passivation ( 200 ). 
     
     
         100 . An arrangement for contacting a semiconductor device having a first substrate ( 100 ) including silicon and a bondable passivation ( 200 ) made of a bondable glass material, the arrangement comprising:
 at least one contact via ( 210 ) extending through the passivation in order to contact a region of the first substrate ( 100 );   an interface ( 204 ) created by anodic bonding between the substrate including silicon and the bondable passivation ( 200 ), wherein silicon-oxygen-silicon bonds are formed in the interface in order to provide adhesion between the passivation ( 200 ) and the substrate ( 100 ).   
     
     
         101 . The arrangement according to  claim 100 , wherein an upper electrode ( 3 ) or an electrode wafer ( 300 ) having recesses therein is provided, wherein the recesses are arranged above the through vias ( 210 ) of the passivation ( 200 ). 
     
     
         102 . The arrangement according to  claim 100 , wherein, for enabling a bonding process, the upper electrode ( 3 ) or the electrode wafer ( 300 ) does not contact the through vias ( 210 ) so that no short circuit occurs. 
     
     
         103 . The arrangement according to  claim 100 , wherein, for contacting:
 a lower bottom plate ( 2 ) is provided,   or an edge pin ( 5 ) is provided via recesses in the electrode wafer ( 300 ) and the passivation ( 200 ) accommodating the same in order to achieve contacting the semiconductor wafer ( 100 ).   
     
     
         104 . The arrangement according to  claim 100 , wherein the arrangement is formed such that the lower semiconductor wafer ( 100 ) can be contacted by the lower bottom plate ( 2 ) or the edge pin ( 5 ), when the edge pin ( 5 ) reaches through a recess in a or the electrode wafer ( 300 ). 
     
     
         105 . The arrangement according to  claim 100 , wherein a metal layer on the passivation ( 200 ) can be contacted by a center pin, and the first substrate ( 100 ) can be contacted via the lower bottom plate ( 2 ), or by the edge pin ( 5 ) via a recess in the passivation ( 200 ). 
     
     
         106 . The arrangement according to  claim 105 , wherein the metal layer is structured such that there is no metal in the position(s) of the contact via(s) ( 210 ).