Inventor · disambiguated record
Robert Osann, Jr.
Also filed as: OSANN JR ROBERT · OSANN ROBERT · OSANN ROBERT JR
25 granted patents·751 citations·filing 1992–2009
97Inventor score
Top patents by PatentIndex Score
25 records- 0196US6613611B1ASIC routing architecture with variable number of custom masksLIGHTSPEED SEMICONDUCTOR CORP·Filed 2000·Granted Sep 2, 2003·125 cites·16 claims
- 0291US6133582AMethods and apparatuses for binning partially completed integrated circuits based upon test resultsLIGHTSPEED SEMICONDUCTOR CORP·Filed 1998·Granted Oct 17, 2000·116 cites·18 claims
- 0389US5383787AIntegrated circuit package with direct access to internal signalsAPTIX CORP·Filed 1993·Granted Jan 24, 1995·125 cites·14 claims
- 0484US7093225B2FPGA with hybrid interconnectOSANN ROBERT JR·Filed 2003·Granted Aug 15, 2006·39 cites·3 claims
- 0584US5414638AProgrammable interconnect architectureAPTIX CORP·Filed 1992·Granted May 9, 1995·48 cites·33 claims
- 0679US6611932B2Method and apparatus for controlling and observing data in a logic block-based ASICLIGHTSPEED SEMICONDUCTOR CORP·Filed 2002·Granted Aug 26, 2003·22 cites·22 claims
- 0776US6769109B2Programmable logic array embedded in mask-programmed ASICLIGHTSPEED SEMICONDUCTOR CORP·Filed 2001·Granted Jul 27, 2004·20 cites·5 claims
- 0876US6694491B1Programmable logic array embedded in mask-programmed ASICLIGHTSPEED SEMICONDUCTOR CORP·Filed 2000·Granted Feb 17, 2004·24 cites·27 claims
- 0976US6223313B1Method and apparatus for controlling and observing data in a logic block-based asicLIGHTSPEED SEMICONDUCTOR CORP·Filed 1997·Granted Apr 24, 2001·38 cites·31 claims
- 1075US6399400B1Methods and apparatuses for binning partially completed integrated circuits based upon test resultsLIGHTSPEED SEMICONDUCTOR CORP·Filed 1999·Granted Jun 4, 2002·40 cites·29 claims
- 1171US7062744B2Emulation solution for programmable instruction DSPOSANN JR ROBERT·Filed 2003·Granted Jun 13, 2006·16 cites·14 claims
- 1270US7703065B2FPGA with hybrid interconnectOSANN JR ROBERT·Filed 2006·Granted Apr 20, 2010·3 cites·5 claims
- 1364US7241635B1Binning for semi-custom ASICsOSANN JR ROBERT·Filed 2003·Granted Jul 10, 2007·9 cites·9 claims
- 1463US8332796B2FPGA with hybrid interconnectOSANN JR ROBERT·Filed 2009·Granted Dec 11, 2012·1 cites·14 claims
- 1563US7055125B2Depopulated programmable logic arrayLIGHTSPEED SEMICONDUCTOR CORP·Filed 2001·Granted May 30, 2006·9 cites·16 claims
- 1663US6150807AIntegrated circuit architecture having an array of test cells providing full controllability for automatic circuit verificationLIGHTSPEED SEMICONDUCTOR CORP·Filed 1999·Granted Nov 21, 2000·20 cites·3 claims
- 1762US5384433APrinted circuit structure including power, decoupling and signal terminationAPTIX CORP·Filed 1993·Granted Jan 24, 1995·32 cites·4 claims
- 1855USRE41548EFPGA with hybrid interconnectOSANN JR ROBERT·Filed 2008·Granted Aug 17, 2010·0 cites·11 claims
- 1954US7679398B2Reprogrammable instruction DSPOSANN JR ROBERT·Filed 2003·Granted Mar 16, 2010·3 cites·26 claims
- 2053US7043713B2Implementing programmable logic array embedded in mask-programmed ASICLIGHTSPEED SEMICONDUCTOR CORP·Filed 2003·Granted May 9, 2006·5 cites·28 claims
- 2152US5640308AField programmable circuit moduleAPTIX CORP·Filed 1995·Granted Jun 17, 1997·21 cites·27 claims
- 2250US6498361B1Design information memory for configurable integrated circuitsLIGHTSPEED SEMICONDUCTOR CORP·Filed 1998·Granted Dec 24, 2002·12 cites·20 claims
- 2346US5872448AIntegrated circuit architecture having an array of test cells providing full controlability for automatic circuit verificationLIGHTSPEED SEMICONDUCTOR CORP·Filed 1996·Granted Feb 16, 1999·10 cites·47 claims
- 2442US6804812B2Depopulated programmable logic arrayLIGHTSPEED SEMICONDUCTOR CORP·Filed 2003·Granted Oct 12, 2004·2 cites·24 claims
- 2540US5506850ALogic analyzer for high channel count applicationsFiled 1994·Granted Apr 9, 1996·11 cites·2 claims
Join the waitlist — get patent alerts
Get an alert when Robert Osann, Jr. files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →