Inventor · disambiguated record
Sabyasachi Das
Also filed as: DAS SABYASACHI
31 granted patents·2 pending applications·220 citations·filing 2001–2023
96Inventor score
Top patents by PatentIndex Score
33 records- 0194US10192016B2Neural network based physical synthesis for circuit designsXILINX INC·Filed 2017·Granted Jan 29, 2019·49 cites·20 claims
- 0292US10303648B1Logical and physical optimizations for partial reconfiguration design flowXILINX INC·Filed 2017·Granted May 28, 2019·11 cites·20 claims
- 0392US9483597B1Opportunistic candidate path selection during physical optimization of a circuit design for an ICXILINX INC·Filed 2015·Granted Nov 1, 2016·12 cites·17 claims
- 0488US10496777B1Physical synthesis for multi-die integrated circuit technologyXILINX INC·Filed 2017·Granted Dec 3, 2019·7 cites·20 claims
- 0588US9773083B1Post-placement and pre-routing processing of critical paths in a circuit designXILINX INC·Filed 2016·Granted Sep 26, 2017·6 cites·20 claims
- 0688US9646126B1Post-routing structural netlist optimization for circuit designsXILINX INC·Filed 2015·Granted May 9, 2017·7 cites·20 claims
- 0787US9965581B1Fanout optimization to facilitate timing improvement in circuit designsXILINX INC·Filed 2015·Granted May 8, 2018·6 cites·20 claims
- 0887US6598215B2Datapath design methodology and routing apparatusINTEL CORP·Filed 2001·Granted Jul 22, 2003·54 cites·43 claims
- 0986US11449660B1Method to perform secondary-PG aware buffering in IC design flowSYNOPSYS INC·Filed 2021·Granted Sep 20, 2022·2 cites·20 claims
- 1085US9836568B1Programmable integrated circuit design flow using timing-driven pipeline analysisXILINX INC·Filed 2016·Granted Dec 5, 2017·6 cites·20 claims
- 1184US10699053B1Timing optimization of memory blocks in a programmable ICXILINX INC·Filed 2018·Granted Jun 30, 2020·5 cites·20 claims
- 1284US8984462B1Physical optimization for timing closure for an integrated circuitXILINX INC·Filed 2014·Granted Mar 17, 2015·8 cites·20 claims
- 1383US9613173B1Interactive multi-step physical synthesisXILINX INC·Filed 2015·Granted Apr 4, 2017·4 cites·20 claims
- 1483US7739324B1Timing driven synthesis of sum-of-product functional blocksCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jun 15, 2010·13 cites·22 claims
- 1579US10068045B1Programmable logic device design implementations with multiplexer transformationsXILINX INC·Filed 2016·Granted Sep 4, 2018·4 cites·20 claims
- 1675US10540463B1Placement of delay circuits for avoiding hold violationsXILINX INC·Filed 2018·Granted Jan 21, 2020·3 cites·20 claims
- 1775US9767247B1Look-up table restructuring for timing closure in circuit designsXILINX INC·Filed 2015·Granted Sep 19, 2017·2 cites·18 claims
- 1872US9235660B1Selective addition of clock buffers to a circuit designXILINX INC·Filed 2014·Granted Jan 12, 2016·3 cites·11 claims
- 1972US8407277B1Full subtractor cell for synthesis of area-efficient subtractor and dividerDAS SABYASACHI·Filed 2008·Granted Mar 26, 2013·5 cites·3 claims
- 2071US12444174B2Rare event training data sets for robust training of semiconductor yield related componentsKLA CORP·Filed 2023·Granted Oct 14, 2025·0 cites·23 claims
- 2171US10572621B1Physical synthesis within placementXILINX INC·Filed 2018·Granted Feb 25, 2020·1 cites·20 claims
- 2269US10839125B1Post-placement and post-routing physical synthesis for multi-die integrated circuitsXILINX INC·Filed 2018·Granted Nov 17, 2020·1 cites·21 claims
- 2369US10565334B1Targeted delay optimization through programmable clock delaysXILINX INC·Filed 2017·Granted Feb 18, 2020·1 cites·20 claims
- 2466US9043735B1Synthesis of fast squarer functional blocksDAS SABYASACHI·Filed 2006·Granted May 26, 2015·4 cites·27 claims
- 2566US8707225B1Synthesis of area-efficient subtractor and divider functional blocksDAS SABYASACHI·Filed 2006·Granted Apr 22, 2014·3 cites·27 claims
- 2664US10242150B1Circuit design implementation using control-set based merging and module-based replicationXILINX INC·Filed 2016·Granted Mar 26, 2019·1 cites·19 claims
- 2761US8996943B2Voltage regulator with by-pass capability for test purposesST MICROELECTRONICS PVT LTD·Filed 2012·Granted Mar 31, 2015·2 cites·15 claims
- 2854US11947885B1Low-power static signoff verification from within an implementation toolSYNOPSYS INC·Filed 2021·Granted Apr 2, 2024·0 cites·20 claims
- 2953US2025165690A1Under test (dut) processing for logic optimizationSYNOPSYS INC·Filed 2023·Application pending·0 cites
- 3049US10528697B1Timing-closure methodology involving clock network in hardware designsXILINX INC·Filed 2017·Granted Jan 7, 2020·0 cites·20 claims
- 3149US2025217222A1Error resolution and auto-correction for unprocessed data recordsCERNER INNOVATION INC·Filed 2023·Application pending·0 cites
- 3247US10970446B1Automated pipeline insertion on a busXILINX INC·Filed 2018·Granted Apr 6, 2021·0 cites·11 claims
- 3346US10642951B1Register pull-out for sequential circuit blocks in circuit designsXILINX INC·Filed 2018·Granted May 5, 2020·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →