Inventor · disambiguated record
Satish Raj
Also filed as: RAJ SATISH · RAJ SATISH SAMUEL
17 granted patents·494 citations·filing 1996–2017
95Inventor score
Files withCADENCE DESIGN SYSTEMS INC11SALOWE JEFFREY SCOTT2CHYAN DAVID1SALOWE JEFFREY S1SYNOPSYS INC1
Top patents by PatentIndex Score
17 records- 0196US8375348B1Method, system, and program product to implement colored tiles for detail routing for double pattern lithographyCADENCE DESIGN SYSTEMS INC·Filed 2010·Granted Feb 12, 2013·41 cites·24 claims
- 0295US8560998B1Method, system, and program product to implement C-routing for double pattern lithographySALOWE JEFFREY SCOTT·Filed 2010·Granted Oct 15, 2013·43 cites·21 claims
- 0393US8671368B1Method, system, and program product to implement detail routing for double pattern lithographySALOWE JEFFREY SCOTT·Filed 2010·Granted Mar 11, 2014·29 cites·30 claims
- 0492US10192021B1Generating and inserting metal and metal etch shapes in a layout to correct design rule errorsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jan 29, 2019·17 cites·20 claims
- 0589US7752590B1Method and mechanism for implementing tessellation-based routingCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jul 6, 2010·20 cites·42 claims
- 0689US6099584ASystem to fix post-layout timing and design rules violationsVSLI TECHNOLOGY INC·Filed 1996·Granted Aug 8, 2000·220 cites·4 claims
- 0788US9384317B1Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniquesCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jul 5, 2016·12 cites·32 claims
- 0887US8640080B1Method and system for visualizing pin access locationsSALOWE JEFFREY S·Filed 2012·Granted Jan 28, 2014·13 cites·27 claims
- 0987US7694261B1Method and mechanism for implementing tessellation-based routingCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Apr 6, 2010·15 cites·49 claims
- 1086US7222322B1Method and mechanism for implementing tessellation-based routingCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted May 22, 2007·39 cites·50 claims
- 1184US9754072B1Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniquesCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Sep 5, 2017·4 cites·20 claims
- 1281US9104830B1Methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Aug 11, 2015·6 cites·20 claims
- 1376US9817941B2Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Nov 14, 2017·4 cites·20 claims
- 1475US6601226B1Tightloop method of timing driven placementSYNOPSYS INC·Filed 2000·Granted Jul 29, 2003·24 cites·41 claims
- 1572US8914763B1Methods, systems, and articles of manufacture for generating multi-layer local maximal orthogonal routing paths in fractured spaceCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Dec 16, 2014·3 cites·23 claims
- 1661US8769467B2Method and system for utilizing hard and preferred rules for C-routing of electronic designsCHYAN DAVID·Filed 2007·Granted Jul 1, 2014·4 cites·23 claims
- 1750US8910107B1Methods, systems, and articles of manufacture for generating multi-layer local maximal orthogonal routing paths in fractured spaceCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Dec 9, 2014·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →