Inventor · disambiguated record
Salil Ravindra Raje
Also filed as: RAJE SALIL · RAJE SALIL R · RAJE SALIL RAVINDRA
19 granted patents·635 citations·filing 1998–2015
96Inventor score
Technology areasG06F
Files withXILINX INC11MONTEREY DESIGN SYSTEMS INC4SYNOPSYS INC2MONTEREY DESIGN SYSTEMS1RAJE SALIL RAVINDRA1
Top patents by PatentIndex Score
19 records- 0193US9864828B1Hardware acceleration device handoff for using programmable integrated circuits as hardware acceleratorsXILINX INC·Filed 2015·Granted Jan 9, 2018·22 cites·20 claims
- 0291US6286128B1Method for design optimization using logical and physical informationMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Sep 4, 2001·202 cites·10 claims
- 0390US7418686B1System for representing the logical and physical information of an integrated circuitXILINX INC·Filed 2005·Granted Aug 26, 2008·21 cites·15 claims
- 0488US7120892B1Process for adjusting data structures of a floorplan upon changes occurringXILINX INC·Filed 2004·Granted Oct 10, 2006·40 cites·12 claims
- 0588US6961916B2Placement method for integrated circuit design using topo-clusteringSYNOPSYS INC·Filed 2002·Granted Nov 1, 2005·45 cites·7 claims
- 0687US6442743B1Placement method for integrated circuit design using topo-clusteringMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Aug 27, 2002·126 cites·13 claims
- 0784US7073149B2System for representing the logical and physical information of an integrated circuitXILINX INC·Filed 2004·Granted Jul 4, 2006·31 cites·19 claims
- 0883US7437695B1Method of memory and run-time efficient hierarchical timing analysis in programmable logic devicesXILINX INC·Filed 2005·Granted Oct 14, 2008·14 cites·10 claims
- 0983US6851099B1Placement method for integrated circuit design using topo-clusteringSYNOPSYS INC·Filed 2000·Granted Feb 1, 2005·28 cites·42 claims
- 1081US7117473B1System for creating a physical hierarchy of a chip without restriction by invading a logical hierarchy of logic blocksXILINX INC·Filed 2004·Granted Oct 3, 2006·23 cites·9 claims
- 1175US7370302B1Partitioning a large design across multiple devicesXILINX INC·Filed 2005·Granted May 6, 2008·5 cites·10 claims
- 1274US7146595B2Data structures for representing the logical and physical information of an integrated circuitXILINX INC·Filed 2004·Granted Dec 5, 2006·16 cites·6 claims
- 1366US7519938B1Strategies for generating an implementation of an electronic designXILINX INC·Filed 2006·Granted Apr 14, 2009·4 cites·18 claims
- 1465US7594212B1Automatic pin placement for integrated circuits to aid circuit board designXILINX INC·Filed 2007·Granted Sep 22, 2009·3 cites·20 claims
- 1564US6775808B1Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuitsMONTEREY DESIGN SYSTEMS INC·Filed 2000·Granted Aug 10, 2004·13 cites·34 claims
- 1659US6651232B1Method and system for progressive clock tree or mesh construction concurrently with physical designMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Nov 18, 2003·35 cites·66 claims
- 1757US6523161B1Method to optimize net lists using simultaneous placement and logic optimizationMONTEREY DESIGN SYSTEMS INC·Filed 2000·Granted Feb 18, 2003·7 cites·42 claims
- 1853US7873927B1Partitioning a large design across multiple devicesXILINX INC·Filed 2008·Granted Jan 18, 2011·0 cites·6 claims
- 1941US8667437B2Creating a standard cell circuit design from a programmable logic device circuit designRAJE SALIL RAVINDRA·Filed 2008·Granted Mar 4, 2014·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →