Inventor · disambiguated record
Sergei Koveshnikov
Also filed as: KOVESHNIKOV SERGEI · KOVESHNIKOV SERGEI V · KOVESHNIKOV SERGEI VIKTOR
23 granted patents·4 pending applications·209 citations·filing 1997–2020
95Inventor score
Top patents by PatentIndex Score
27 records- 0194US9761599B2Integrated structures containing vertically-stacked memory cellsMICRON TECHNOLOGY INC·Filed 2015·Granted Sep 12, 2017·9 cites·22 claims
- 0291US6339011B1Method of forming semiconductive active area having a proximity gettering region therein and method of processing a monocrystalline silicon substrate to have a proximity gettering regionMICRON TECHNOLOGY INC·Filed 2001·Granted Jan 15, 2002·59 cites·41 claims
- 0386US10381365B2Integrated structures containing vertically-stacked memory cellsMICRON TECHNOLOGY INC·Filed 2017·Granted Aug 13, 2019·3 cites·5 claims
- 0476US6620632B2Method for evaluating impurity concentrations in semiconductor substratesSEH AMERICA INC·Filed 2000·Granted Sep 16, 2003·18 cites·17 claims
- 0573US6673147B2High resistivity silicon wafer having electrically inactive dopant and method of producing sameSEH AMERICA INC·Filed 2001·Granted Jan 6, 2004·16 cites·33 claims
- 0671US11309321B2Integrated structures containing vertically-stacked memory cellsMICRON TECHNOLOGY INC·Filed 2020·Granted Apr 19, 2022·0 cites·9 claims
- 0771US6669777B2Method of producing a high resistivity silicon wafer utilizing heat treatment that occurs during device fabricationSEH AMERICA INC·Filed 2001·Granted Dec 30, 2003·9 cites·19 claims
- 0870US6565652B1High resistivity silicon wafer and method of producing same using the magnetic field Czochralski methodSEH AMERICA INC·Filed 2001·Granted May 20, 2003·8 cites·11 claims
- 0964US10892268B2Integrated structures containing vertically-stacked memory cellsMICRON TECHNOLOGY INC·Filed 2019·Granted Jan 12, 2021·0 cites·3 claims
- 1061US6576501B1Double side polished wafers having external gettering sites, and method of producing sameSEH AMERICA INC·Filed 2002·Granted Jun 10, 2003·8 cites·18 claims
- 1161US6346460B1Low cost silicon substrate with impurity gettering and latch up protection and method of manufactureSEH AMERICA·Filed 1999·Granted Feb 12, 2002·25 cites·19 claims
- 1260US6583024B1High resistivity silicon wafer with thick epitaxial layer and method of producing sameSEH AMERICA INC·Filed 2001·Granted Jun 24, 2003·7 cites·20 claims
- 1359US6630363B2Method for evaluating impurity concentrations in unpolished wafers grown by the Czochralski methodSEH AMERICA INC·Filed 2001·Granted Oct 7, 2003·4 cites·9 claims
- 1459US5943552ASchottky metal detection methodSEH AMERICA INC·Filed 1997·Granted Aug 24, 1999·30 cites·24 claims
- 1556US6649427B2Method for evaluating impurity concentrations in epitaxial susceptorsSEH AMERICA INC·Filed 2001·Granted Nov 18, 2003·3 cites·5 claims
- 1653US6423556B1Method for evaluating impurity concentrations in heat treatment furnacesSEH AMERICA INC·Filed 2001·Granted Jul 23, 2002·2 cites·9 claims
- 1752US6632688B2Method for evaluating impurity concentrations in epitaxial reagent gasesSEH AMERICA INC·Filed 2001·Granted Oct 14, 2003·2 cites·4 claims
- 1849US6794227B2Method of producing an SOI waferSEH AMERICA INC·Filed 2002·Granted Sep 21, 2004·2 cites·19 claims
- 1949US6669775B2High resistivity silicon wafer produced by a controlled pull rate czochralski methodSEH AMERICA INC·Filed 2001·Granted Dec 30, 2003·1 cites·16 claims
- 2043US7507521B2Silicon based optically degraded arc for lithographic patterningINTEL CORP·Filed 2004·Granted Mar 24, 2009·2 cites·15 claims
- 2143US6896727B2Method of determining nitrogen concentration within a waferSEH AMERICA INC·Filed 2002·Granted May 24, 2005·0 cites·20 claims
- 2237US2004259321A1Reducing processing induced stressFiled 2003·Application pending·0 cites
- 2335US11018149B2Building stacked hollow channels for a three dimensional circuit deviceINTEL CORP·Filed 2014·Granted May 25, 2021·0 cites·1 claims
- 2435US2004010394A1Systems, methods and computer program products for determining contaminant concentrations in semiconductor materialsSEH AMERICA INC·Filed 2002·Application pending·0 cites
- 2533US2003224603A1Double side polished wafers having external gettering sites, and method of producing sameFiled 2003·Application pending·0 cites
- 2633US2003224135A1Double side polished wafers having external gettering sites, and method of producing sameFiled 2003·Application pending·0 cites
- 2731US7687225B2Optical coatingsINTEL CORP·Filed 2004·Granted Mar 30, 2010·1 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →