Inventor · disambiguated record
Sean Teehan
Also filed as: TEEHAN SEAN
70 granted patents·3 pending applications·501 citations·filing 2014–2024
99Inventor score
Top patents by PatentIndex Score
73 records- 0199US9620590B1Nanosheet channel-to-source and drain isolationIBM·Filed 2016·Granted Apr 11, 2017·105 cites·13 claims
- 0299US9608065B1Air gap spacer for metal gatesIBM·Filed 2016·Granted Mar 28, 2017·141 cites·20 claims
- 0398US11043581B2Nanosheet channel-to-source and drain isolationTESSERA INC·Filed 2020·Granted Jun 22, 2021·4 cites·11 claims
- 0498US9905643B1Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistorsIBM·Filed 2016·Granted Feb 27, 2018·28 cites·18 claims
- 0598US9450095B1Single spacer for complementary metal oxide semiconductor process flowIBM·Filed 2016·Granted Sep 20, 2016·24 cites·16 claims
- 0698US9362179B1Method to form dual channel semiconductor material finsIBM·Filed 2015·Granted Jun 7, 2016·41 cites·14 claims
- 0796US11652161B2Nanosheet channel-to-source and drain isolationTESSERA LLC·Filed 2021·Granted May 16, 2023·2 cites·21 claims
- 0896US10074730B2Forming stacked nanowire semiconductor deviceIBM·Filed 2016·Granted Sep 11, 2018·11 cites·17 claims
- 0995US10211055B2Fin patterns with varying spacing without fin cutIBM·Filed 2018·Granted Feb 19, 2019·7 cites·11 claims
- 1095US10014391B2Vertical transport field effect transistor with precise gate length definitionIBM·Filed 2016·Granted Jul 3, 2018·10 cites·10 claims
- 1195US9917196B1Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2016·Granted Mar 13, 2018·8 cites·8 claims
- 1295US9842739B2Method and structure for enabling high aspect ratio sacrificial gatesIBM·Filed 2016·Granted Dec 12, 2017·8 cites·16 claims
- 1395US9728622B1Dummy gate formation using spacer pull down hardmaskIBM·Filed 2016·Granted Aug 8, 2017·11 cites·18 claims
- 1495US9318574B2Method and structure for enabling high aspect ratio sacrificial gatesIBM·Filed 2014·Granted Apr 19, 2016·16 cites·15 claims
- 1594US10615269B2Nanosheet channel-to-source and drain isolationIBM·Filed 2018·Granted Apr 7, 2020·5 cites·12 claims
- 1694US10381437B2Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2017·Granted Aug 13, 2019·6 cites·11 claims
- 1794US10249738B2Nanosheet channel-to-source and drain isolationIBM·Filed 2016·Granted Apr 2, 2019·6 cites·9 claims
- 1893US11239316B2Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2019·Granted Feb 1, 2022·4 cites·20 claims
- 1992US11127815B2Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2019·Granted Sep 21, 2021·4 cites·20 claims
- 2092US10043801B2Air gap spacer for metal gatesIBM·Filed 2017·Granted Aug 7, 2018·5 cites·20 claims
- 2191US2025142856A1Nanosheet channel-to-source and drain isolationADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Application pending·0 cites
- 2290US9786666B2Method to form dual channel semiconductor material finsIBM·Filed 2016·Granted Oct 10, 2017·5 cites·13 claims
- 2390US9659779B2Method and structure for enabling high aspect ratio sacrificial gatesIBM·Filed 2014·Granted May 23, 2017·7 cites·16 claims
- 2489US10833190B2Super long channel device within VFET architectureIBM·Filed 2019·Granted Nov 10, 2020·4 cites·15 claims
- 2589US9536744B1Enabling large feature alignment marks with sidewall image transfer patterningIBM·Filed 2015·Granted Jan 3, 2017·5 cites·14 claims
- 2686US12166110B2Nanosheet channel-to-source and drain isolationADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Dec 10, 2024·0 cites·23 claims
- 2786US11557589B2Air gap spacer for metal gatesTESSERA LLC·Filed 2020·Granted Jan 17, 2023·1 cites·17 claims
- 2885US10607991B2Air gap spacer for metal gatesTESSERA INC·Filed 2018·Granted Mar 31, 2020·2 cites·20 claims
- 2985US9991117B2Fin patterns with varying spacing without fin cutIBM·Filed 2017·Granted Jun 5, 2018·2 cites·20 claims
- 3085US9984877B2Fin patterns with varying spacing without fin cutIBM·Filed 2017·Granted May 29, 2018·2 cites·20 claims
- 3184US9893166B2Dummy gate formation using spacer pull down hardmaskIBM·Filed 2017·Granted Feb 13, 2018·3 cites·20 claims
- 3282US12402403B2Air gap spacer for metal gatesADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Aug 26, 2025·0 cites·20 claims
- 3382US10249762B2Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistorsIBM·Filed 2018·Granted Apr 2, 2019·2 cites·20 claims
- 3482US9953915B2Electrically conductive interconnect including via having increased contact surface areaIBM·Filed 2016·Granted Apr 24, 2018·3 cites·18 claims
- 3581US9754942B2Single spacer for complementary metal oxide semiconductor process flowIBM·Filed 2016·Granted Sep 5, 2017·2 cites·18 claims
- 3680US10083962B2Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer depositionIBM·Filed 2016·Granted Sep 25, 2018·2 cites·14 claims
- 3780US9997369B2Margin for fin cut using self-aligned triple patterningIBM·Filed 2016·Granted Jun 12, 2018·2 cites·20 claims
- 3880US9985138B2Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistorsIBM·Filed 2017·Granted May 29, 2018·2 cites·19 claims
- 3979US11869937B2Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2022·Granted Jan 9, 2024·0 cites·17 claims
- 4079US10217634B2Fin patterns with varying spacing without fin cutIBM·Filed 2018·Granted Feb 26, 2019·1 cites·12 claims
- 4179US9768075B1Method and structure to enable dual channel fin critical dimension controlIBM·Filed 2016·Granted Sep 19, 2017·2 cites·18 claims
- 4277US11869936B2Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2021·Granted Jan 9, 2024·0 cites·16 claims
- 4377US10629698B2Method and structure for enabling high aspect ratio sacrificial gatesIBM·Filed 2017·Granted Apr 21, 2020·1 cites·15 claims
- 4475US10026615B2Fin patterns with varying spacing without Fin cutIBM·Filed 2016·Granted Jul 17, 2018·1 cites·11 claims
- 4574US10553581B2Air gap spacer for metal gatesIBM·Filed 2016·Granted Feb 4, 2020·1 cites·17 claims
- 4672US9748146B1Single spacer for complementary metal oxide semiconductor process flowIBM·Filed 2016·Granted Aug 29, 2017·1 cites·20 claims
- 4771US9553044B2Electrically conductive interconnect including via having increased contact surface areaIBM·Filed 2014·Granted Jan 24, 2017·2 cites·10 claims
- 4870US10242882B2Cyclic etch process to remove dummy gate oxide layer for fin field effect transistor fabricationIBM·Filed 2017·Granted Mar 26, 2019·1 cites·16 claims
- 4969US11646235B2Vertical tunneling field effect transistor with dual liner bottom spacerIBM·Filed 2021·Granted May 9, 2023·0 cites·5 claims
- 5069US10424663B2Super long channel device within VFET architectureIBM·Filed 2017·Granted Sep 24, 2019·1 cites·9 claims
Showing the top 50 of 73 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →