Inventor · disambiguated record
Shinichi Iketani
Also filed as: IKETANI SHINICHI
26 granted patents·12 pending applications·29 citations·filing 2014–2024
93Inventor score
Top patents by PatentIndex Score
38 records- 0192US9781830B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2014·Granted Oct 3, 2017·11 cites·13 claims
- 0289US10820427B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2019·Granted Oct 27, 2020·4 cites·16 claims
- 0384US10201085B2Methods of forming blind vias for printed circuit boardsSANMINA CORP·Filed 2018·Granted Feb 5, 2019·4 cites·18 claims
- 0484US9781844B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2014·Granted Oct 3, 2017·5 cites·20 claims
- 0579US11399439B2Methods of forming high aspect ratio plated through holes and high precision stub removal in a printed circuit boardSANMINA CORP·Filed 2019·Granted Jul 26, 2022·2 cites·4 claims
- 0679US10188001B2Methods of forming high aspect ratio plated through holes and high precision stub removal in a printed circuit boardSANMINA CORP·Filed 2015·Granted Jan 22, 2019·3 cites·13 claims
- 0777US11549184B2Coating of nano-scaled cavitiesAVERATEK CORP·Filed 2021·Granted Jan 10, 2023·0 cites·21 claims
- 0874US2024407106A1Catalyzed Metal Foil and Uses ThereofAVERATEK CORP·Filed 2024·Application pending·0 cites
- 0973US2023345642A1Asymmetrical electrolytic plating for a conductive patternAVERATEK CORP·Filed 2023·Application pending·0 cites
- 1073US2021307177A1Systems and methods for manufacturingAVERATEK CORP·Filed 2021·Application pending·0 cites
- 1171US2022418113A1Systems and methods for manufacturingAVERATEK CORP·Filed 2022·Application pending·0 cites
- 1270US11142825B2Coating of nano-scaled cavitiesAVERATEK CORP·Filed 2020·Granted Oct 12, 2021·0 cites·18 claims
- 1369US11765827B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2020·Granted Sep 19, 2023·0 cites·8 claims
- 1469US11304311B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2020·Granted Apr 12, 2022·0 cites·14 claims
- 1567US12150254B2Method of forming a laminate structure having a plated through-hole using a removable cover layerSANMINA CORP·Filed 2020·Granted Nov 19, 2024·0 cites·8 claims
- 1667US2021243903A1Ultra thin dielectric printed circuit boards with thin laminates and method of manufacturing thereofSANMINA CORP·Filed 2021·Application pending·0 cites
- 1764US2021045252A1Systems and methods for manufacturingAVERATEK CORP·Filed 2020·Application pending·0 cites
- 1863US2021345498A1Three dimensional circuit formationAVERATEK CORP·Filed 2021·Application pending·0 cites
- 1962US12063748B2Catalyzed metal foil and uses thereof to produce electrical circuitsAVERATEK CORP·Filed 2021·Granted Aug 13, 2024·0 cites·14 claims
- 2062US10811210B2Multilayer printed circuit board via hole registration and accuracySANMINA CORP·Filed 2019·Granted Oct 20, 2020·0 cites·6 claims
- 2161US11877404B2Catalyzed metal foil and uses thereofAVERATEK CORP·Filed 2021·Granted Jan 16, 2024·0 cites·18 claims
- 2261US11716819B2Asymmetrical electrolytic plating for a conductive patternAVERATEK CORP·Filed 2019·Granted Aug 1, 2023·0 cites·13 claims
- 2361US11076492B2Three dimensional circuit formationAVERATEK CORP·Filed 2019·Granted Jul 27, 2021·0 cites·14 claims
- 2460US10993333B2Methods of manufacturing ultra thin dielectric printed circuit boards with thin laminatesSANMINA CORP·Filed 2018·Granted Apr 27, 2021·0 cites·10 claims
- 2560US10362687B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2018·Granted Jul 23, 2019·0 cites·6 claims
- 2659US10757819B2Method of forming a laminate structure having a plated through-hole using a removable cover layerSANMINA CORP·Filed 2014·Granted Aug 25, 2020·0 cites·15 claims
- 2759US10667390B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2017·Granted May 26, 2020·0 cites·9 claims
- 2858US2015181724A1Methods of forming segmented vias for printed circuit boardsSANMINA CORP·Filed 2014·Application pending·0 cites
- 2957US10123432B2Simultaneous and selective wide gap partitioning of via structures using plating resistSANMINA CORP·Filed 2017·Granted Nov 6, 2018·0 cites·14 claims
- 3055US2018317327A1Methods of forming segmented vias for printed circuit boardsSANMINA CORP·Filed 2018·Application pending·0 cites
- 3155US2020190670A1Nano metal film depositionAVERATEK CORP·Filed 2019·Application pending·0 cites
- 3253US11246226B2Laminate structures with hole plugs and methods of forming laminate structures with hole plugsSANMINA CORP·Filed 2019·Granted Feb 8, 2022·0 cites·14 claims
- 3353US10446356B2Multilayer printed circuit board via hole registration and accuracySANMINA CORP·Filed 2017·Granted Oct 15, 2019·0 cites·12 claims
- 3453US2019394888A1Patterning of electroless metalsAVERATEK CORP·Filed 2019·Application pending·0 cites
- 3552US9661758B2Methods of segmented through hole formation using dual diameter through hole edge trimmingSANMINA CORP·Filed 2014·Granted May 23, 2017·0 cites·10 claims
- 3649US2020232098A1Pattern formation using catalyst blockerAVERATEK CORP·Filed 2020·Application pending·0 cites
- 3747US12213258B2Method of manufacture for embedded IC chip directly connected to PCBAVERATEK CORP·Filed 2019·Granted Jan 28, 2025·0 cites·11 claims
- 3846US10237983B2Method for forming hole plugSANMINA CORP·Filed 2015·Granted Mar 19, 2019·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →