Inventor · disambiguated record
Shishir Kumar
Also filed as: KUMAR SHISHIR
34 granted patents·3 pending applications·72 citations·filing 2006–2025
95Inventor score
Top patents by PatentIndex Score
37 records- 0192US9006841B2Dual port SRAM having reduced cell size and rectangular shapeKUMAR SHISHIR·Filed 2012·Granted Apr 14, 2015·41 cites·9 claims
- 0286US11742045B2Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memoryST MICROELECTRONICS INT NV·Filed 2021·Granted Aug 29, 2023·2 cites·16 claims
- 0385US10283191B1Method and circuit for adaptive read-write operation in self-timed memoryST MICROELECTRONICS INT NV·Filed 2018·Granted May 7, 2019·6 cites·15 claims
- 0483US11532633B2Dual port memory cell with improved access resistanceST MICROELECTRONICS INT NV·Filed 2021·Granted Dec 20, 2022·1 cites·20 claims
- 0580US10191902B2Method and unit for building semantic rule for a semantic dataWIPRO LTD·Filed 2016·Granted Jan 29, 2019·3 cites·14 claims
- 0678US7545180B2Sense amplifier providing low capacitance with reduced resolution timeST MICROELECTRONICS PVT LTD·Filed 2007·Granted Jun 9, 2009·11 cites·20 claims
- 0778US2025321675A1Localized and relocatable software placement and noc-based access to memory controllersXILINX INC·Filed 2025·Application pending·0 cites
- 0876US11889675B2Dual port memory cell with improved access resistanceST MICROELECTRONICS INT NV·Filed 2022·Granted Jan 30, 2024·0 cites·19 claims
- 0975US10998077B2Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memoryST MICROELECTRONICS INT NV·Filed 2019·Granted May 4, 2021·3 cites·21 claims
- 1074US10073838B2Method and system for enabling verifiable semantic rule building for semantic dataWIPRO LTD·Filed 2016·Granted Sep 11, 2018·2 cites·13 claims
- 1170US12353717B2Localized and relocatable software placement and NoC-based access to memory controllersXILINX INC·Filed 2022·Granted Jul 8, 2025·0 cites·20 claims
- 1265US12457056B1Intelligent management of forward error correctionCISCO TECH INC·Filed 2024·Granted Oct 28, 2025·0 cites·20 claims
- 1364US11152376B2Dual port memory cell with improved access resistanceST MICROELECTRONICS INT NV·Filed 2018·Granted Oct 19, 2021·1 cites·17 claims
- 1459US9165642B2Low voltage dual supply memory cell with two word lines and activation circuitryST MICROELECTRONICS INT NV·Filed 2013·Granted Oct 20, 2015·2 cites·21 claims
- 1558US12316326B1Delay circuitSYNOPSYS INC·Filed 2023·Granted May 27, 2025·0 cites·14 claims
- 1657US12272424B2Reducing spurious write operations in a memory deviceSYNOPSYS INC·Filed 2023·Granted Apr 8, 2025·0 cites·17 claims
- 1756US12094513B2Power supply tracking circuitry for embedded memoriesSYNOPSYS INC·Filed 2022·Granted Sep 17, 2024·0 cites·20 claims
- 1852US12340864B2Interface level-shifter dual-rail memory architectureSYNOPSYS INC·Filed 2023·Granted Jun 24, 2025·0 cites·19 claims
- 1952US12112818B2Scan chain compression for testing memory of a system on a chipSYNOPSYS INC·Filed 2022·Granted Oct 8, 2024·0 cites·20 claims
- 2050US12019908B2Dynamically allocated buffer poolingXILINX INC·Filed 2021·Granted Jun 25, 2024·0 cites·20 claims
- 2149US10706915B2Method and circuit for adaptive read-write operation in self-timed memoryST MICROELECTRONICS INT NV·Filed 2019·Granted Jul 7, 2020·0 cites·21 claims
- 2249US9147453B2Programmable delay introducing circuit in self timed memoryST MICROELECTRONICS INT NV·Filed 2014·Granted Sep 29, 2015·0 cites·17 claims
- 2348US12354656B2Reducing memory device bitline leakageSYNOPSYS INC·Filed 2022·Granted Jul 8, 2025·0 cites·20 claims
- 2448US9898527B2Methods for retrieving information and devices thereofWIPRO LTD·Filed 2014·Granted Feb 20, 2018·0 cites·17 claims
- 2547US2025322863A1Voltage calibration for write operationSYNOPSYS INC·Filed 2024·Application pending·0 cites
- 2646US10311944B2SRAM read multiplexer including replica transistorsST MICROELECTRONICS INT NV·Filed 2018·Granted Jun 4, 2019·0 cites·21 claims
- 2745US11025252B2Circuit for detection of single bit upsets in generation of internal clock for memoryST MICROELECTRONICS INT NV·Filed 2019·Granted Jun 1, 2021·0 cites·25 claims
- 2845US8963053B2Programmable delay introducing circuit in self-timed memoryKOHLI NISHU·Filed 2012·Granted Feb 24, 2015·0 cites·14 claims
- 2942US10037794B1SRAM read multiplexer including replica transistorsST MICROELECTRONICS INT NV·Filed 2017·Granted Jul 31, 2018·0 cites·17 claims
- 3040US9590602B2System and method for a pulse generatorST MICROELECTRONICS INT NV·Filed 2014·Granted Mar 7, 2017·0 cites·33 claims
- 3140US8138455B2Programmable delay introducing circuit in self timed memoryKOHLI NISHU·Filed 2006·Granted Mar 20, 2012·0 cites·6 claims
- 3239US9910880B2System and method for managing enterprise user groupKUMAR SHISHIR·Filed 2014·Granted Mar 6, 2018·0 cites·18 claims
- 3338US11521697B2Circuit and method for at speed detection of a word line fault condition in a memory circuitST MICROELECTRONICS INT NV·Filed 2020·Granted Dec 6, 2022·0 cites·22 claims
- 3438US11195576B2Robust adaptive method and circuit for controlling a timing window for enabling operation of sense amplifierST MICROELECTRONICS INT NV·Filed 2019·Granted Dec 7, 2021·0 cites·20 claims
- 3538US9324414B2Selective dual cycle write operation for a self-timed memoryST MICROELECTRONICS INT NV·Filed 2013·Granted Apr 26, 2016·0 cites·24 claims
- 3637US2017032025A1System and method for performing verifiable query on semantic dataWIPRO LTD·Filed 2015·Application pending·0 cites
- 3736US11393532B2Circuit and method for at speed detection of a word line fault condition in a memory circuitST MICROELECTRONICS INT NV·Filed 2020·Granted Jul 19, 2022·0 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →