Inventor · disambiguated record
Stephen G. Burger
Also filed as: BURGER STEPHEN · BURGER STEPHEN G
17 granted patents·942 citations·filing 1990–2001
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
17 records- 0194US6430670B1Apparatus and method for a virtual hashed page tableHEWLETT PACKARD CO·Filed 2000·Granted Aug 6, 2002·86 cites·26 claims
- 0287US6088780APage table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual addressINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Jul 11, 2000·141 cites·35 claims
- 0383US6393544B1Method and apparatus for calculating a page table index from a virtual addressINST THE DEV OF EMERGING ARCHI·Filed 1999·Granted May 21, 2002·113 cites·20 claims
- 0479US5940872ASoftware and hardware-managed translation lookaside bufferINTEL CORP·Filed 1996·Granted Aug 17, 1999·89 cites·20 claims
- 0577US6199144B1Method and apparatus for transferring data in a computer systemINTEL CORP·Filed 1997·Granted Mar 6, 2001·77 cites·20 claims
- 0677US5535352AAccess hints for input/output address translation mechanismsHEWLETT PACKARD CO·Filed 1994·Granted Jul 9, 1996·79 cites·9 claims
- 0774US6128706AApparatus and method for a load bias--load with intent to semaphoreINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Oct 3, 2000·68 cites·15 claims
- 0869US6408373B2Method and apparatus for pre-validating regions in a virtual addressing schemeINST THE DEV OF EMERGING ARCHI·Filed 2001·Granted Jun 18, 2002·12 cites·7 claims
- 0969US6286095B1Computer apparatus having special instructions to force ordered load and store operationsHEWLETT PACKARD CO·Filed 1995·Granted Sep 4, 2001·61 cites·8 claims
- 1066US5915117AComputer architecture for the deferral of exceptions on speculative instructionsINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Jun 22, 1999·49 cites·34 claims
- 1163US6216214B1Apparatus and method for a virtual hashed page tableINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Apr 10, 2001·34 cites·17 claims
- 1262US6006325AMethod and apparatus for instruction and data serialization in a computer processorINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Dec 21, 1999·39 cites·17 claims
- 1352US5515522ACoherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cacheHEWLETT PACKARD CO·Filed 1994·Granted May 7, 1996·25 cites·21 claims
- 1448US6079012AComputer that selectively forces ordered execution of store and load operations between a CPU and a shared memoryHEWLETT PACKARD CO·Filed 1997·Granted Jun 20, 2000·22 cites·8 claims
- 1545US5784708ATranslation mechanism for input/output addressesHEWLETT PACKARD CO·Filed 1996·Granted Jul 21, 1998·19 cites·11 claims
- 1642US6230248B1Method and apparatus for pre-validating regions in a virtual addressing schemeINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted May 8, 2001·14 cites·1 claims
- 1740US5278985ASoftware method for implementing dismissible instructions on a computerHEWLETT PACKARD CO·Filed 1990·Granted Jan 11, 1994·14 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →