Inventor · disambiguated record
Stanislav Shwartsman
Also filed as: SHWARTSMAN STANISLAV
49 granted patents·9 pending applications·180 citations·filing 2008–2024
98Inventor score
Top patents by PatentIndex Score
58 records- 0198US11977886B2Systems, methods, and apparatuses for tile storeINTEL CORP·Filed 2022·Granted May 7, 2024·7 cites·20 claims
- 0298US11714642B2Systems, methods, and apparatuses for tile storeINTEL CORP·Filed 2022·Granted Aug 1, 2023·7 cites·19 claims
- 0398US11086623B2Systems, methods, and apparatuses for tile matrix multiplication and accumulationINTEL CORP·Filed 2017·Granted Aug 10, 2021·32 cites·20 claims
- 0496US11567765B2Systems, methods, and apparatuses for tile loadINTEL CORP·Filed 2017·Granted Jan 31, 2023·8 cites·20 claims
- 0595US11360770B2Systems, methods, and apparatuses for zeroing a matrixINTEL CORP·Filed 2017·Granted Jun 14, 2022·7 cites·20 claims
- 0695US11288069B2Systems, methods, and apparatuses for tile storeINTEL CORP·Filed 2017·Granted Mar 29, 2022·7 cites·17 claims
- 0795US11263008B2Systems, methods, and apparatuses for tile broadcastINTEL CORP·Filed 2017·Granted Mar 1, 2022·7 cites·20 claims
- 0894US11321469B2Microprocessor pipeline circuitry to support cryptographic computingINTEL CORP·Filed 2019·Granted May 3, 2022·5 cites·24 claims
- 0993US9335943B2Method and apparatus for fine grain memory protectionINTEL CORP·Filed 2014·Granted May 10, 2016·21 cites·24 claims
- 1092US8972697B2Gather using index array and finite state machineSPERBER ZEEV·Filed 2012·Granted Mar 3, 2015·17 cites·26 claims
- 1192US2025117222A1Systems, methods, and apparatuses for tile matrix multiplication and accumulationINTEL CORP·Filed 2024·Application pending·0 cites
- 1290US12147804B2Systems, methods, and apparatuses for tile matrix multiplication and accumulationINTEL CORP·Filed 2021·Granted Nov 19, 2024·1 cites·21 claims
- 1390US2025004716A1Systems, methods, and apparatuses for tile loadINTEL CORP·Filed 2024·Application pending·0 cites
- 1489US12086591B2Device, method and system to predict an address collision by a load and a storeINTEL CORP·Filed 2021·Granted Sep 10, 2024·3 cites·20 claims
- 1589US2024192954A1Systems, methods, and apparatuses for matrix operationsINTEL CORP·Filed 2024·Application pending·0 cites
- 1688US8352683B2Method and system to reduce the power consumption of a memory deviceINTEL CORP·Filed 2010·Granted Jan 8, 2013·12 cites·16 claims
- 1785US12182571B2Systems, methods, and apparatuses for tile load, multiplication and accumulationINTEL CORP·Filed 2023·Granted Dec 31, 2024·0 cites·20 claims
- 1883US10152451B2Scatter using index array and finite state machineINTEL CORP·Filed 2017·Granted Dec 11, 2018·3 cites·8 claims
- 1983US9753889B2Gather using index array and finite state machineINTEL CORP·Filed 2015·Granted Sep 5, 2017·3 cites·17 claims
- 2082US11580031B2Hardware for split data translation lookaside buffersINTEL CORP·Filed 2020·Granted Feb 14, 2023·2 cites·24 claims
- 2182US2022300286A1Systems, methods, and apparatuses for zeroing a matrixINTEL CORP·Filed 2022·Application pending·0 cites
- 2281US9552169B2Apparatus and method for efficient memory renaming prediction using virtual registersINTEL CORP·Filed 2015·Granted Jan 24, 2017·4 cites·26 claims
- 2378US10146737B2Gather using index array and finite state machineINTEL CORP·Filed 2015·Granted Dec 4, 2018·2 cites·18 claims
- 2478US9626333B2Scatter using index array and finite state machineSPERBER ZEEV·Filed 2012·Granted Apr 18, 2017·5 cites·22 claims
- 2577US9792222B2Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structureINTEL CORP·Filed 2014·Granted Oct 17, 2017·4 cites·10 claims
- 2677US2022138329A1Microprocessor pipeline circuitry to support cryptographic computingINTEL CORP·Filed 2022·Application pending·0 cites
- 2775US10754655B2Automatic predication of hard-to-predict convergent branchesINTEL CORP·Filed 2018·Granted Aug 25, 2020·2 cites·18 claims
- 2874US12216581B2System, method, and apparatus for enhanced pointer identification and prefetchingINTEL CORP·Filed 2023·Granted Feb 4, 2025·0 cites·20 claims
- 2973US10402263B2Accelerating memory fault resolution by performing fast re-fetchingINTEL CORP·Filed 2017·Granted Sep 3, 2019·1 cites·20 claims
- 3072US12106100B2Systems, methods, and apparatuses for matrix operationsINTEL CORP·Filed 2017·Granted Oct 1, 2024·0 cites·19 claims
- 3172US9268697B2Snoop filter having centralized translation circuitry and shadow tag arrayPARDO ILAN·Filed 2012·Granted Feb 23, 2016·3 cites·20 claims
- 3269US10719355B2Criticality based port schedulingINTEL CORP·Filed 2018·Granted Jul 21, 2020·1 cites·20 claims
- 3369US8990512B2Method and apparatus for error correction in a cacheINTEL CORP·Filed 2012·Granted Mar 24, 2015·2 cites·24 claims
- 3469US8271732B2System and method to reduce power consumption by partially disabling cache memoryCOHEN EHUD·Filed 2008·Granted Sep 18, 2012·5 cites·20 claims
- 3567US10761844B2Systems and methods to predict load data valuesINTEL CORP·Filed 2018·Granted Sep 1, 2020·1 cites·25 claims
- 3667US9501132B2Instruction and logic for store broadcast and power managementINTEL CORP·Filed 2014·Granted Nov 22, 2016·2 cites·20 claims
- 3766US11693780B2System, method, and apparatus for enhanced pointer identification and prefetchingINTEL CORP·Filed 2021·Granted Jul 4, 2023·0 cites·18 claims
- 3866US10579530B2Prefetch filter cache for a processorINTEL CORP·Filed 2016·Granted Mar 3, 2020·1 cites·19 claims
- 3963US9690640B2Recovery from multiple data errorsINTEL CORP·Filed 2013·Granted Jun 27, 2017·1 cites·17 claims
- 4063US8914617B2Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical registerRAIKIN SHLOMO·Filed 2010·Granted Dec 16, 2014·2 cites·20 claims
- 4160US11150979B2Accelerating memory fault resolution by performing fast re-fetchingINTEL CORP·Filed 2019·Granted Oct 19, 2021·0 cites·20 claims
- 4258US11080194B2System, method, and apparatus for enhanced pointer identification and prefetchingINTEL CORP·Filed 2018·Granted Aug 3, 2021·0 cites·24 claims
- 4355US9405545B2Method and apparatus for cutting senior store latency using store prefetchingSHWARTSMAN STANISLAV·Filed 2011·Granted Aug 2, 2016·1 cites·22 claims
- 4454US9411728B2Methods and apparatus for efficient communication between caches in hierarchical caching designSHALEV RON·Filed 2011·Granted Aug 9, 2016·1 cites·22 claims
- 4553US12468631B2Region aware delta prefetcherINTEL CORP·Filed 2021·Granted Nov 11, 2025·0 cites·25 claims
- 4652US2025103509A1Microarchitecture and instruction set architecture extensions for efficient iso-area victim buffering through translation lookaside buffer partitioningINTEL CORP·Filed 2023·Application pending·0 cites
- 4750US9558127B2Instruction and logic for a cache prefetcher and dataless fill bufferINTEL CORP·Filed 2014·Granted Jan 31, 2017·0 cites·17 claims
- 4849US10467011B2Thread pause processors, methods, systems, and instructionsINTEL CORP·Filed 2014·Granted Nov 5, 2019·0 cites·12 claims
- 4949US9292362B2Method and apparatus to protect a processor against excessive power usageINTEL CORP·Filed 2013·Granted Mar 22, 2016·0 cites·20 claims
- 5048US10095522B2Instruction and logic for register based hardware memory renamingINTEL CORP·Filed 2014·Granted Oct 9, 2018·0 cites·20 claims
Showing the top 50 of 58 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →