Systems, methods, and apparatuses for zeroing a matrix

Abstract

Embodiments detailed herein relate to matrix operations. In particular, performing a matrix operation of zeroing a matrix in response to a single instruction. For example, a processor detailed which includes decode circuitry to decode an instruction having fields for an opcode and a source/destination matrix operand identifier; and execution circuitry to execute the decoded instruction to zero each data element of the identified source/destination matrix.

We claim: 
     
         1 . A processor comprising:
 decode circuitry to decode an instruction having fields for an opcode and a source/destination matrix operand identifier; and   execution circuitry to execute the decoded instruction to zero each data element of the identified source/destination matrix.   
     
     
         2 . The processor of  claim 1 , wherein the execution circuitry is to zero each row of the source/destination matrix operand. 
     
     
         3 . The processor of  claim 1 , wherein the source/destination matrix operand is a plurality of registers configured to represent a matrix. 
     
     
         4 . The processor of  claim 1 , wherein the execution circuitry to fault upon a determination the source/destination matrix operand identifier is not configured as a matrix. 
     
     
         5 . The processor of  claim 1 , wherein the execution circuitry is to set a status bit regarding the identified source/destination matrix as being zero. 
     
     
         6 . A method comprising:
 decoding an instruction having fields for an opcode and a source/destination matrix operand identifier; and   executing the decoded instruction to zero each data element of the identified source/destination matrix.   
     
     
         7 . The method of  claim 6 , wherein the zeroing is done a row of the source/destination matrix operand at a time. 
     
     
         8 . The method of  claim 6 , wherein the source/destination matrix operand is a plurality of registers configured to represent a matrix. 
     
     
         9 . The method of  claim 6 , further comprising:
 faulting upon a determination the source/destination matrix operand identifier is not configured as a matrix.   
     
     
         10 . The method of  claim 6 , further comprising:
 setting a status bit regarding the identified source/destination matrix as being zero.   
     
     
         11 . A non-transitory machine-readable medium storing an instruction which causes a processor to perform a method, the method comprising:
 decoding the instruction having fields for an opcode and a source/destination matrix operand identifier; and   executing the decoded instruction to zero each data element of the identified source/destination matrix.   
     
     
         12 . The non-transitory machine-readable medium of  claim 11 , wherein the zeroing is done a row of the source/destination matrix operand at a time. 
     
     
         13 . The non-transitory machine-readable medium of  claim 11 , wherein the source/destination matrix operand is a plurality of registers configured to represent a matrix. 
     
     
         14 . The non-transitory machine-readable medium of  claim 11 , further comprising:
 faulting upon a determination the source/destination matrix operand identifier is not configured as a matrix.   
     
     
         15 . The non-transitory machine-readable medium of  claim 11 , further comprising:
 setting a status bit regarding the identified source/destination matrix as being zero.   
     
     
         16 . A system comprising:
 a processor; and   an accelerator coupled to the processor, the accelerator including:
 decode circuitry to decode an instruction having fields for an opcode and a source/destination matrix operand identifier; and 
 execution circuitry to execute the decoded instruction to zero each data element of the identified source/destination matrix. 
   
     
     
         17 . The system of  claim 16 , wherein the execution circuitry is to zero each row of the source/destination matrix operand. 
     
     
         18 . The system of  claim 16 , wherein the source/destination matrix operand is a plurality of registers configured to represent a matrix. 
     
     
         19 . The system of  claim 16 , wherein the execution circuitry to fault upon a determination the source/destination matrix operand identifier is not configured as a matrix. 
     
     
         20 . The system of  claim 16 , wherein the execution circuitry is to set a status bit regarding the identified source/destination matrix as being zero.