Inventor · disambiguated record
Sunfei Fang
Also filed as: FANG SUNFEI
40 granted patents·11 pending applications·394 citations·filing 2001–2012
98Inventor score
Files withIBM35FANG SUNFEI3SAMSUNG ELECTRONICS CO LTD3CHIDAMBARRAO DURESETI2INFINEON TECHNOLOGIES AG2
Top patents by PatentIndex Score
51 records- 0197US7151023B1Metal gate MOSFET by full semiconductor metal alloy conversionIBM·Filed 2005·Granted Dec 19, 2006·80 cites·14 claims
- 0295US8629022B2Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating sameCHIDAMBARRAO DURESETI·Filed 2012·Granted Jan 14, 2014·18 cites·19 claims
- 0392US7067368B1Method for forming self-aligned dual salicide in CMOS technologiesIBM·Filed 2005·Granted Jun 27, 2006·17 cites·10 claims
- 0490US7482215B2Self-aligned dual segment liner and method of manufacturing the sameIBM·Filed 2006·Granted Jan 27, 2009·20 cites·14 claims
- 0587US6784105B1Simultaneous native oxide removal and metal neutral deposition methodINFINEON TECHNOLOGIES CORP·Filed 2003·Granted Aug 31, 2004·45 cites·16 claims
- 0686US7488660B2Extended raised source/drain structure for enhanced contact area and method for forming extended raised source/drain structureIBM·Filed 2006·Granted Feb 10, 2009·13 cites·10 claims
- 0785US8445974B2Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating sameCHIDAMBARRAO DURESETI·Filed 2010·Granted May 21, 2013·7 cites·19 claims
- 0885US6818519B2Method of forming organic spacers and using organic spacers to form semiconductor device featuresINFINEON TECHNOLOGIES AG·Filed 2002·Granted Nov 16, 2004·27 cites·12 claims
- 0982US7582516B2CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxyIBM·Filed 2006·Granted Sep 1, 2009·10 cites·18 claims
- 1081US7105440B2Self-forming metal silicide gate for CMOS devicesIBM·Filed 2005·Granted Sep 12, 2006·9 cites·19 claims
- 1180US7785950B2Dual stress memory technique method and related structureIBM·Filed 2005·Granted Aug 31, 2010·9 cites·13 claims
- 1279US8039382B2Method for forming self-aligned metal silicide contactsIBM·Filed 2009·Granted Oct 18, 2011·6 cites·10 claims
- 1379US7271455B2Formation of fully silicided metal gate using dual self-aligned silicide processIBM·Filed 2004·Granted Sep 18, 2007·20 cites·9 claims
- 1478US7122472B2Method for forming self-aligned dual fully silicided gates in CMOS devicesIBM·Filed 2004·Granted Oct 17, 2006·23 cites·36 claims
- 1577US7618891B2Method for forming self-aligned metal silicide contactsIBM·Filed 2006·Granted Nov 17, 2009·6 cites·22 claims
- 1677US7517767B2Forming conductive stud for semiconductive devicesIBM·Filed 2006·Granted Apr 14, 2009·6 cites·3 claims
- 1777US7393746B2Post-silicide spacer removalIBM·Filed 2006·Granted Jul 1, 2008·6 cites·6 claims
- 1877US7220662B2Fully silicided field effect transistorsIBM·Filed 2005·Granted May 22, 2007·7 cites·18 claims
- 1977US7112481B2Method for forming self-aligned dual salicide in CMOS technologiesIBM·Filed 2005·Granted Sep 26, 2006·5 cites·20 claims
- 2075US7999332B2Asymmetric semiconductor devices and method of fabricatingIBM·Filed 2009·Granted Aug 16, 2011·5 cites·18 claims
- 2174US7309901B2Field effect transistors (FETs) with multiple and/or staircase silicideIBM·Filed 2005·Granted Dec 18, 2007·5 cites·9 claims
- 2272US7923365B2Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereonSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Apr 12, 2011·4 cites·15 claims
- 2370US7598572B2Silicided polysilicon spacer for enhanced contact areaIBM·Filed 2006·Granted Oct 6, 2009·4 cites·2 claims
- 2470US6916729B2Salicide formation methodIBM·Filed 2003·Granted Jul 12, 2005·16 cites·11 claims
- 2569US7785999B2Formation of fully silicided metal gate using dual self-aligned silicide processIBM·Filed 2007·Granted Aug 31, 2010·3 cites·11 claims
- 2667US8173531B2Structure and method to improve threshold voltage of MOSFETS including a high K dielectricFANG SUNFEI·Filed 2009·Granted May 8, 2012·3 cites·19 claims
- 2766US7585773B2Non-conformal stress liner for enhanced MOSFET performanceIBM·Filed 2006·Granted Sep 8, 2009·3 cites·8 claims
- 2866US7541288B2Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniquesSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Jun 2, 2009·2 cites·23 claims
- 2965US8679938B2Shallow trench isolation for device including deep trench capacitorsFANG SUNFEI·Filed 2012·Granted Mar 25, 2014·2 cites·20 claims
- 3064US7317204B2Test structure of semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Jan 8, 2008·2 cites·28 claims
- 3159US7816219B2Field effect transistors (FETs) with multiple and/or staircase silicideIBM·Filed 2007·Granted Oct 19, 2010·1 cites·13 claims
- 3259US6872652B2Method of cleaning an inter-level dielectric interconnectINFINEON TECHNOLOGIES AG·Filed 2001·Granted Mar 29, 2005·6 cites·22 claims
- 3356US8039331B2Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistorsIBM·Filed 2008·Granted Oct 18, 2011·0 cites·8 claims
- 3454US7064025B1Method for forming self-aligned dual salicide in CMOS technologiesIBM·Filed 2004·Granted Jun 20, 2006·4 cites·21 claims
- 3552US7410852B2Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistorsIBM·Filed 2006·Granted Aug 12, 2008·0 cites·1 claims
- 3651US7863693B2Forming conductive stud for semiconductive devicesIBM·Filed 2008·Granted Jan 4, 2011·0 cites·5 claims
- 3750US2007034967A1Metal gate mosfet by full semiconductor metal alloy conversionIBM·Filed 2006·Application pending·0 cites
- 3849US8866261B2Self-aligned silicide bottom plate for eDRAM applications by self-diffusing metal in CVD/ALD metal processIBM·Filed 2012·Granted Oct 21, 2014·0 cites·12 claims
- 3948US8513085B2Structure and method to improve threshold voltage of MOSFETs including a high k dielectricFANG SUNFEI·Filed 2012·Granted Aug 20, 2013·0 cites·20 claims
- 4047US2014120687A1Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal ProcessIBM·Filed 2012·Application pending·0 cites
- 4146US7504309B2Pre-silicide spacer removalIBM·Filed 2006·Granted Mar 17, 2009·0 cites·6 claims
- 4245US2010029072A1Methods of Forming Electrical Interconnects Using Thin Electrically Insulating Liners in Contact HolesPARK JAE-EON·Filed 2009·Application pending·0 cites
- 4344US2004219743A1Method of forming organic spacers and using organic spacers to form semiconductor device featuresFiled 2004·Application pending·0 cites
- 4444US2008179638A1Gap fill for underlapped dual stress linersIBM·Filed 2007·Application pending·0 cites
- 4542US2009017586A1Channel stress modification by capped metal-semiconductor layer volume changeIBM·Filed 2007·Application pending·0 cites
- 4641US2008185645A1Semiconductor structure including stepped source/drain regionIBM·Filed 2007·Application pending·0 cites
- 4740US2009014807A1Dual stress liners for integrated circuitsCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 4839US2011156110A1Field Effect Transistors Having Gate Electrode Silicide Layers with Reduced Surface DamageKIM JUN-JUNG·Filed 2011·Application pending·0 cites
- 4939US2007254420A1Source/drain implantation and channel strain transfer using different sized spacers and related semiconductor deviceIBM·Filed 2006·Application pending·0 cites
- 5037US7223691B2Method of forming low resistance and reliable via in inter-level dielectric interconnectIBM·Filed 2004·Granted May 29, 2007·0 cites·10 claims
Showing the top 50 of 51 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →