Field Effect Transistors Having Gate Electrode Silicide Layers with Reduced Surface Damage

Abstract

Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.

1 . A semiconductor integrated circuit device comprising:
 a gate insulating film formed on a semiconductor substrate;   a gate electrode formed on the gate insulating film;   a source/drain region aligned with the gate electrode; and   silicide layers formed on the source/drain region and a top surface of the gate electrode, respectively,   wherein the surface damage of the silicide layer formed on the source/drain region is less than that of the silicide layer formed on the top surface of the gate electrode.   
     
     
         2 . The device of  claim 1 , wherein the silicide layer on the source/drain region is separated a predetermined distance away from the gate electrode, and a portion of a surface of the semiconductor substrate on which the silicide layer is not formed is more damaged than a surface of the silicide layer on the source/drain region. 
     
     
         3 . The device of  claim 2 , further comprising a first spacer extending from a side surface of the gate electrode to a portion of a top surface of the semiconductor substrate on which the silicide layer is not formed. 
     
     
         4 . The device of  claim 3 , wherein the first spacer is an oxide film. 
     
     
         5 . The device of  claim 1 , further comprising a stress layer covering the gate electrode and the semiconductor substrate.