Inventor · disambiguated record
Tanausu Ramirez
Also filed as: RAMIREZ TANAUSU
12 granted patents·4 pending applications·38 citations·filing 2011–2017
88Inventor score
Top patents by PatentIndex Score
16 records- 0184US9071281B2Selective provision of error correction for memoryINTEL CORP·Filed 2013·Granted Jun 30, 2015·10 cites·23 claims
- 0280US9112537B2Content-aware caches for reliabilityRAMIREZ TANAUSU·Filed 2011·Granted Aug 18, 2015·8 cites·22 claims
- 0379US10440195B2Calibrating a media advance system of a page wide array printing deviceHEWLETT PACKARD DEVELOPMENT CO·Filed 2015·Granted Oct 8, 2019·2 cites·15 claims
- 0472US9043659B2Banking of reliability metricsINTEL CORP·Filed 2012·Granted May 26, 2015·3 cites·17 claims
- 0571US9075904B2Vulnerability estimation for cache memoryINTEL CORP·Filed 2013·Granted Jul 7, 2015·3 cites·22 claims
- 0670US9170947B2Recovering from data errors using implicit redundancyVERA XAVIER·Filed 2011·Granted Oct 27, 2015·3 cites·23 claims
- 0768US9405647B2Register error protection through binary translationVERA XAVIER·Filed 2011·Granted Aug 2, 2016·2 cites·19 claims
- 0867US9176895B2Increased error correction for cache memories through adaptive replacement policiesINTEL CORP·Filed 2013·Granted Nov 3, 2015·2 cites·17 claims
- 0962US9286172B2Fault-aware mapping for shared last level cache (LLC)RAMIREZ TANAUSU·Filed 2011·Granted Mar 15, 2016·3 cites·24 claims
- 1060US9608922B2Traffic control on an on-chip networkMONCHIERO MATTEO·Filed 2011·Granted Mar 28, 2017·1 cites·11 claims
- 1158US9983880B2Method and apparatus for improved thread selectionINTEL CORP·Filed 2014·Granted May 29, 2018·1 cites·16 claims
- 1249US2016342495A1Register error protection through binary translationINTEL CORP·Filed 2016·Application pending·0 cites
- 1348US2017201459A1Traffic control on an on-chip networkINTEL CORP·Filed 2017·Application pending·0 cites
- 1444US9619309B2Enforcing different operational configurations for different tasks for failure rate based control of processorsINTEL CORP·Filed 2012·Granted Apr 11, 2017·0 cites·23 claims
- 1540US2016011874A1Silent memory instructions and miss-rate tracking to optimize switching policy on threads in a processing deviceORENSTEIN DORON·Filed 2014·Application pending·0 cites
- 1637US2014237018A1Tracking distributed execution on on-chip multinode networks without a centralized mechanismMONCHIERO MATTEO·Filed 2011·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Tanausu Ramirez files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →