Traffic control on an on-chip network

Abstract

An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.

What is claimed is: 
     
         1 . A method of controlling traffic on an on-chip network, the method comprising:
 injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network;   receiving the packet at a second node coupled to the on-chip network;   modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change;   returning the packet with the bit modified to the first node by the second node; and   changing the first rate by the first node in response to detecting that the bit in the packet was modified.   
     
     
         2 . The method of  claim 1 , wherein determining by the second node that a rate at which packets are injected into the on-chip network should change comprises determining that the first rate should be reduced. 
     
     
         3 . The method of  claim 2 , wherein determining that the first rate should be reduced comprises determining that the second node lacks resources to handle the packet at the time the second node receives the packet. 
     
     
         4 . The method of  claim 2 , wherein determining that the first rate should be reduced comprises determining that a number of packets deflected by the second node exceeds a threshold number. 
     
     
         5 . The method of  claim 1 , wherein the second node is a destination node for the packet. 
     
     
         6 . The method of  claim 1 , wherein the second node is an intermediate node to forward the packet to a destination node. 
     
     
         7 . The method of  claim 1 , wherein returning the packet to the first node comprises transmitting the packet to the first node via a pre-defined route. 
     
     
         8 . The method of  claim 7 , wherein the pre-defined route is a route the packet took from the first node to the second node. 
     
     
         9 . The method of  claim 1 , wherein returning the packet to the first node comprises transmitting the packet to the first node via a random route. 
     
     
         10 . The method of  claim 1 , wherein the on-chip network is a buffered network. 
     
     
         11 . An apparatus comprising:
 a node coupled to an on-chip network, wherein the node is to
 receive a packet from a source node, 
 determine whether a rate at which the source node injects packets into the on-chip network should change, 
 modify a bit in the received packet in response to determining that the rate at which the source node injects packets into the on-chip network should change, and 
 transmitting the packet with the bit modified to the source node; and 
   the source node, wherein the source node is to change the rate at which the source node injects packets into the on-chip network in response to detecting that the bit in the packet was modified.   
     
     
         12 . The apparatus of  claim 11 , wherein determining whether a rate at which the source node injects packets into the on-chip network should change comprises determining that the rate at which the source node injects packets into the on-chip network should be reduced. 
     
     
         13 . The apparatus of  claim 12 , wherein determining that the rate at which the source node injects packets into the on-chip network should be reduced comprises determining that the node receiving the packet lacks resources to handle the packet. 
     
     
         14 . The apparatus of  claim 12 , wherein determining that the rate at which the source node injects packets into the on-chip network should be reduced comprises determining that a number of packets deflected by the node receiving the packet exceeds a threshold number. 
     
     
         15 . The apparatus of  claim 11 , wherein the node receiving the packet is a destination node for the packet. 
     
     
         16 . The apparatus of  claim 11 , wherein the node receiving the packet is an intermediate node to forward the packet to the packet's destination node. 
     
     
         17 . The apparatus of  claim 11 , wherein transmitting the packet with the bit modified to the source node comprises transmitting the packet to the source node via a pre-defined route. 
     
     
         18 . The apparatus of  claim 17 , wherein the pre-defined route is a route the packet took from the source node to the node receiving the packet. 
     
     
         19 . The apparatus of  claim 11 , wherein transmitting the packet with the bit modified to the source node comprises transmitting the packet to the source node via a random route. 
     
     
         20 . The apparatus of  claim 11 , wherein the on-chip network is a buffered network.