Inventor · disambiguated record
Xavier Vera
Also filed as: VERA XAVIER
29 granted patents·5 pending applications·180 citations·filing 2005–2017
96Inventor score
Top patents by PatentIndex Score
34 records- 0192US8074110B2Enhancing reliability of a many-core processorVERA XAVIER·Filed 2006·Granted Dec 6, 2011·37 cites·24 claims
- 0290US8151094B2Dynamically estimating lifetime of a semiconductor deviceVERA XAVIER·Filed 2005·Granted Apr 3, 2012·23 cites·19 claims
- 0389US8291168B2Disabling cache portions during low voltage operationsWILKERSON CHRISTOPHER·Filed 2011·Granted Oct 16, 2012·12 cites·20 claims
- 0484US9071281B2Selective provision of error correction for memoryINTEL CORP·Filed 2013·Granted Jun 30, 2015·10 cites·23 claims
- 0582US7447054B2NBTI-resilient memory cells with NAND gatesINTEL CORP·Filed 2006·Granted Nov 4, 2008·14 cites·20 claims
- 0681US8103830B2Disabling cache portions during low voltage operationsWILKERSON CHRISTOPHER·Filed 2008·Granted Jan 24, 2012·9 cites·20 claims
- 0780US9112537B2Content-aware caches for reliabilityRAMIREZ TANAUSU·Filed 2011·Granted Aug 18, 2015·8 cites·22 claims
- 0880US8090996B2Detecting soft errors via selective re-executionVERA XAVIER·Filed 2006·Granted Jan 3, 2012·9 cites·21 claims
- 0975US7689804B2Selectively protecting a register fileINTEL CORP·Filed 2006·Granted Mar 30, 2010·7 cites·22 claims
- 1074US9678878B2Disabling cache portions during low voltage operationsWILKERSON CHRISTOPHER·Filed 2012·Granted Jun 13, 2017·3 cites·5 claims
- 1174US7600145B2Clustered variations-aware architectureINTEL CORP·Filed 2005·Granted Oct 6, 2009·7 cites·27 claims
- 1274US7558992B2Reducing the soft error vulnerability of stored dataINTEL CORP·Filed 2005·Granted Jul 7, 2009·7 cites·21 claims
- 1372US9043659B2Banking of reliability metricsINTEL CORP·Filed 2012·Granted May 26, 2015·3 cites·17 claims
- 1471US10528473B2Disabling cache portions during low voltage operationsINTEL CORP·Filed 2017·Granted Jan 7, 2020·1 cites·13 claims
- 1571US9075904B2Vulnerability estimation for cache memoryINTEL CORP·Filed 2013·Granted Jul 7, 2015·3 cites·22 claims
- 1671US7747913B2Correcting intermittent errors in data storage structuresINTEL CORP·Filed 2007·Granted Jun 29, 2010·5 cites·10 claims
- 1770US9170947B2Recovering from data errors using implicit redundancyVERA XAVIER·Filed 2011·Granted Oct 27, 2015·3 cites·23 claims
- 1868US9405647B2Register error protection through binary translationVERA XAVIER·Filed 2011·Granted Aug 2, 2016·2 cites·19 claims
- 1968US8069376B2On-line testing for decode logicMONFERRER PEDRO CHAPARRO·Filed 2009·Granted Nov 29, 2011·4 cites·20 claims
- 2068US7577015B2Memory content inverting to minimize NTBI effectsINTEL CORP·Filed 2007·Granted Aug 18, 2009·4 cites·9 claims
- 2167US9176895B2Increased error correction for cache memories through adaptive replacement policiesINTEL CORP·Filed 2013·Granted Nov 3, 2015·2 cites·17 claims
- 2262US9286172B2Fault-aware mapping for shared last level cache (LLC)RAMIREZ TANAUSU·Filed 2011·Granted Mar 15, 2016·3 cites·24 claims
- 2361US8352812B2Protecting data storage structures from intermittent errorsINTEL CORP·Filed 2007·Granted Jan 8, 2013·2 cites·5 claims
- 2460US9608922B2Traffic control on an on-chip networkMONCHIERO MATTEO·Filed 2011·Granted Mar 28, 2017·1 cites·11 claims
- 2551US8402310B2Detecting soft errors via selective re-executionVERA XAVIER·Filed 2011·Granted Mar 19, 2013·0 cites·20 claims
- 2649US2016342495A1Register error protection through binary translationINTEL CORP·Filed 2016·Application pending·0 cites
- 2748US8477558B2Memory apparatuses with low supply voltagesABELLA JAUME·Filed 2008·Granted Jul 2, 2013·0 cites·22 claims
- 2848US2017201459A1Traffic control on an on-chip networkINTEL CORP·Filed 2017·Application pending·0 cites
- 2945US2009150653A1Mechanism for soft error detection and recovery in issue queuesMONFERRER PEDRO CHAPARRO·Filed 2007·Application pending·0 cites
- 3044US9619309B2Enforcing different operational configurations for different tasks for failure rate based control of processorsINTEL CORP·Filed 2012·Granted Apr 11, 2017·0 cites·23 claims
- 3144US8578137B2Reducing aging effect on registersABELLA JAUME·Filed 2006·Granted Nov 5, 2013·1 cites·27 claims
- 3242US2006288196A1System and method for exploiting timing variability in a processor pipelineUNSAL OSMAN·Filed 2005·Application pending·0 cites
- 3337US2014237018A1Tracking distributed execution on on-chip multinode networks without a centralized mechanismMONCHIERO MATTEO·Filed 2011·Application pending·0 cites
- 3435US10020037B2Capacity register fileABELLA JAUME·Filed 2007·Granted Jul 10, 2018·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →