Register error protection through binary translation

Abstract

Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.

1 . A processor comprising:
 a plurality of registers; and   an instruction generation logic to generate at least one instruction to periodically read information from at least one register of the plurality of registers in order to detect whether the at least one register of the plurality of registers contains erroneous information.   
     
     
         2 . A processor as recited in  claim 1 , further comprising a detection logic to detect at least one register of the plurality registers that is to store information that will not be accessed for longer than a threshold period based, at least in part, on at least a portion of a code being translated by a binary translator. 
     
     
         3 . A processor as recited in  claim 2 , wherein the instruction generation logic is to generate the at least one instruction to periodically read information from the at least one register detected by the detection logic. 
     
     
         4 . A processor as recited in  claim 2 , further comprising:
 an analysis logic to analyze at least a portion of the code being translated by the binary translator; and   wherein the detection logic is to detect the at least one register that is to store the information that will not be accessed for longer than the threshold period based, at least in part, on a result of an analysis performed by the analysis logic.   
     
     
         5 . A processor as recited in  claim 2 , wherein the detection logic is to detect the at least one register that is to store the information that will not be accessed for longer than the threshold period based, at least in part, on dynamic profiling of at least a portion of the code by the binary translator. 
     
     
         6 . A processor as recited in  claim 2 , wherein the threshold period is programmable. 
     
     
         7 . A system comprising:
 a memory;   a processor coupled to the memory, the processor comprising:   a plurality of registers; and   an instruction generation logic to generate at least one instruction to periodically move information from at least one register of the plurality of registers to at least one other register of the plurality of registers in order to help prevent the information from becoming corrupt.   
     
     
         8 . A system as recited in  claim 7 , the processor further comprising a detection logic to detect at least one register of the plurality registers that is to store information that will not be accessed for longer than a threshold period based, at least in part, on at least a portion of a code being translated by a binary translator. 
     
     
         9 . A system as recited in  claim 8 , wherein the instruction generation logic generates the at least one instruction to periodically move information from the at least one register detected by the detection logic. 
     
     
         10 . A system as recited in  claim 8 , the processor further comprising:
 an analysis logic to analyze at least a portion of the code being translated by the binary translator; and   wherein the detection logic is to detect the at least one register that is to store the information that will not be accessed for longer than the threshold period based, at least in part, on a result of an analysis performed by the analysis logic.   
     
     
         11 . A system as recited in  claim 8 , wherein the detection is based, at least in part, on dynamic profiling of at least a portion of the code by the binary translator. 
     
     
         12 . A system as recited in  claim 8 , wherein the threshold period is programmable. 
     
     
         13 . A processor comprising:
 a plurality of registers; and   a logic to cause information stored in at least one of the plurality of registers to be stored into a memory location based at least in part on a determination that the information will be stored in the at least one of the plurality of registers for at least a threshold period.   
     
     
         14 . A processor as recited in  claim 13 , further comprising a detection logic to detect at least one register of the plurality registers that is to store information that will not be accessed for longer than a threshold period based, at least in part, on at least a portion of a code being translated by a binary translator. 
     
     
         15 . A processor as recited in  claim 14 , wherein the instruction generation logic generates at least one instruction to cause information stored in the at least one register detected by the detection logic to be stored into a memory location. 
     
     
         16 . A processor as recited in  claim 14 , further comprising:
 an analysis logic to analyze at least a portion of the code being translated by the binary translator; and   wherein the detection logic detects the at least one register that is to store the information that will not be accessed for longer than the threshold period based, at least in part, on a result of an analysis performed by the analysis logic.   
     
     
         17 . A processor as recited in  claim 14 , wherein the detection is based, at least in part, on dynamic profiling of at least a portion of the code by the binary translator. 
     
     
         18 . A processor as recited in  claim 14 , wherein the threshold period is programmable.