Inventor · disambiguated record
Tom Herrmann
Also filed as: HERRMANN TOM
19 granted patents·4 pending applications·65 citations·filing 2011–2024
91Inventor score
Files withGLOBALFOUNDRIES INC10GLOBALFOUNDRIES US INC6BALDAUF TIM3GLOBALFOUNDRIES DRESDEN MOD 12FLACHOWSKY STEFAN1
Top patents by PatentIndex Score
23 records- 0197US9583640B1Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structureGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 28, 2017·30 cites·20 claims
- 0291US10121846B1Resistor structure with high resistance based on very thin semiconductor layerGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 6, 2018·10 cites·19 claims
- 0389US8912606B2Integrated circuits having protruding source and drain regions and methods for forming integrated circuitsBALDAUF TIM·Filed 2012·Granted Dec 16, 2014·16 cites·14 claims
- 0484US11315949B2Charge-trapping sidewall spacer-type non-volatile memory device and methodGLOBALFOUNDRIES DRESDEN MOD 1·Filed 2020·Granted Apr 26, 2022·2 cites·20 claims
- 0576US8580643B2Threshold voltage adjustment in a Fin transistor by corner implantationBALDAUF TIM·Filed 2011·Granted Nov 12, 2013·4 cites·20 claims
- 0668US2024055434A1Structure including transistor using buried insulator layer as gate dielectric and trench isolations in source and drainGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 0767US11837605B2Structure including transistor using buried insulator layer as gate dielectric and trench isolations in source and drainGLOBALFOUNDRIES US INC·Filed 2021·Granted Dec 5, 2023·0 cites·7 claims
- 0866US10580863B2Transistor element with reduced lateral electrical fieldGLOBALFOUNDRIES INC·Filed 2017·Granted Mar 3, 2020·1 cites·2 claims
- 0964US9711513B2Semiconductor structure including a nonvolatile memory cell and method for the formation thereofGLOBALFOUNDRIES INC·Filed 2015·Granted Jul 18, 2017·1 cites·15 claims
- 1062US11929433B2Asymmetric FET for FDSOI devicesGLOBALFOUNDRIES US INC·Filed 2021·Granted Mar 12, 2024·0 cites·16 claims
- 1162US10283584B2Capacitive structure in a semiconductor device having reduced capacitance variabilityGLOBALFOUNDRIES INC·Filed 2016·Granted May 7, 2019·1 cites·20 claims
- 1254US11245032B2Asymmetric FET for FDSOI devicesGLOBALFOUNDRIES US INC·Filed 2019·Granted Feb 8, 2022·0 cites·12 claims
- 1354US2025279349A1Capacitive junction between conductive line and conductive pillar with methods to form sameGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 1451US8916928B2Threshold voltage adjustment in a fin transistor by corner implantationGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 23, 2014·0 cites·17 claims
- 1549US2025133735A1Nonvolatile memory with isolation structure and method of forming the sameGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 1647US11610999B2Floating-gate devices in high voltage applicationsGLOBALFOUNDRIES DRESDEN MOD 1·Filed 2020·Granted Mar 21, 2023·0 cites·20 claims
- 1746US10283642B1Thin body field effect transistor including a counter-doped channel area and a method of forming the sameGLOBALFOUNDRIES INC·Filed 2018·Granted May 7, 2019·0 cites·15 claims
- 1845US10644152B1Buried-channel low noise transistors and methods of making such devicesGLOBALFOUNDRIES INC·Filed 2019·Granted May 5, 2020·0 cites·20 claims
- 1943US10497803B2Fully depleted silicon on insulator (FDSOI) lateral double-diffused metal oxide semiconductor (LDMOS) for high frequency applicationsGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 3, 2019·0 cites·20 claims
- 2042US8859408B2Stabilized metal silicides in silicon-germanium regions of transistor elementsFLACHOWSKY STEFAN·Filed 2011·Granted Oct 14, 2014·0 cites·17 claims
- 2139US2013230948A1Multiple step implant process for forming source/drain regions on semiconductor devicesSCHEIPER THILO·Filed 2012·Application pending·0 cites
- 2237US8941187B2Strain engineering in three-dimensional transistors based on strained isolation materialBALDAUF TIM·Filed 2012·Granted Jan 27, 2015·0 cites·8 claims
- 2335US10930777B2Laterally double diffused metal oxide semiconductor (LDMOS) device on fully depleted silicon on insulator (FDSOI) enabling high input voltageGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 23, 2021·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →