Inventor · disambiguated record
Tung-Hsing Lee
Also filed as: LEE TUNG-HSING
33 granted patents·26 pending applications·121 citations·filing 2004–2025
96Inventor score
Files withMEDIATEK INC36LEE TUNG-HSING5GLOBALFOUNDRIES US INC4UNITED MICROELECTRONICS CORP4KO CHING-CHUNG3
Top patents by PatentIndex Score
59 records- 0191US7897995B2Lateral bipolar junction transistor with reduced base resistanceMEDIATEK INC·Filed 2009·Granted Mar 1, 2011·21 cites·17 claims
- 0289US9324705B2Lateral bipolar junction transistorMEDIATEK INC·Filed 2014·Granted Apr 26, 2016·8 cites·5 claims
- 0389US7671469B2SiGe device with SiGe-embedded dummy pattern for alleviating micro-loading effectMEDIATEK INC·Filed 2007·Granted Mar 2, 2010·16 cites·13 claims
- 0487US9640489B2Seal ring structure with capacitorMEDIATEK INC·Filed 2014·Granted May 2, 2017·7 cites·24 claims
- 0587US8212323B2Seal ring structure for integrated circuitsLEE TUNG-HSING·Filed 2010·Granted Jul 3, 2012·9 cites·25 claims
- 0686US9543232B2Semiconductor package structure and method for forming the sameMEDIATEK INC·Filed 2015·Granted Jan 10, 2017·4 cites·18 claims
- 0786US8810001B2Seal ring structure with capacitorHUNG CHENG-CHOU·Filed 2012·Granted Aug 19, 2014·9 cites·11 claims
- 0884US7932581B2Lateral bipolar junction transistorMEDIATEK INC·Filed 2009·Granted Apr 26, 2011·10 cites·22 claims
- 0981US9620640B2Body-contact metal-oxide-semiconductor field effect transistor deviceMEDIATEK INC·Filed 2014·Granted Apr 11, 2017·5 cites·32 claims
- 1077US8674454B2Lateral bipolar junction transistorKO CHING-CHUNG·Filed 2009·Granted Mar 18, 2014·5 cites·14 claims
- 1175US8043919B2Method of fabricating semiconductor deviceUNITED MICROELECTRONICS CORP·Filed 2007·Granted Oct 25, 2011·7 cites·18 claims
- 1274US8860544B2Integrated inductorKO CHING-CHUNG·Filed 2009·Granted Oct 14, 2014·6 cites·8 claims
- 1372US12480987B2Dynamic voltage stress condition optimization method and dynamic voltage stress condition optimization system capable of performing block-based dynamic voltage stress wafer testing processMEDIATEK INC·Filed 2024·Granted Nov 25, 2025·0 cites·20 claims
- 1469US9190976B2Passive device cell and fabrication process thereofMEDIATEK INC·Filed 2013·Granted Nov 17, 2015·2 cites·16 claims
- 1568US2025224443A1Dynamic Voltage Stress Condition Optimization Method and Dynamic Voltage Stress Condition Optimization System Capable of Performing Block-based Dynamic Voltage Stress Wafer Testing ProcessMEDIATEK INC·Filed 2025·Application pending·0 cites
- 1667US2025148271A1Adaptive Minimum Voltage Aging Margin Prediction Method and Adaptive Minimum Voltage Aging Margin Prediction System Capable of Providing Satisfactory Prediction AccuracyMEDIATEK INC·Filed 2024·Application pending·0 cites
- 1766US11011303B2Dummy fill with eddy current self-canceling element for inductor componentGLOBALFOUNDRIES US INC·Filed 2018·Granted May 18, 2021·1 cites·19 claims
- 1864US8987851B2Radio-frequency device package and method for fabricating the sameMEDIATEK INC·Filed 2013·Granted Mar 24, 2015·1 cites·9 claims
- 1964US2025148273A1System and method for utilizing transformer deep learning based outlier ic detectionMEDIATEK INC·Filed 2024·Application pending·0 cites
- 2063US8084769B2Testkey design pattern for gate oxideTING SHYH-FANN·Filed 2007·Granted Dec 27, 2011·2 cites·10 claims
- 2163US2024230755A9Outlier Integrated Circuit Detection Method and Outlier Integrated Circuit Detection System by Using Machine Learning FrameworksMEDIATEK INC·Filed 2023·Application pending·0 cites
- 2262US2025174497A1Die-Level Parametric Prediction Boosting Method and System for Improving Prediction Accuracy by Incorporating Physical Location Parametric DataMEDIATEK INC·Filed 2024·Application pending·0 cites
- 2361US2025174498A1Die-Level Parametric Prediction Boosting Method and Die-Level Parametric Prediction Boosting System for Improving Prediction Accuracy by Incorporating a Wafer Map DistributionMEDIATEK INC·Filed 2024·Application pending·0 cites
- 2460US2025176278A1Electrostatic discharge protection deviceMEDIATEK INC·Filed 2024·Application pending·0 cites
- 2560US2025173286A1Cross-die Interconnection Monitor Method and Cross-die Interconnection Monitor System Capable of Extracting Cross-die Interconnection Data for Multi-die PackagesMEDIATEK INC·Filed 2024·Application pending·0 cites
- 2659US7588991B2Method for fabricating embedded static random access memoryUNITED MICROELECTRONICS CORP·Filed 2007·Granted Sep 15, 2009·1 cites·22 claims
- 2759US7250332B2Method for fabricating a semiconductor device having improved hot carrier immunity abilityUNITED MICROELECTRONICS CORP·Filed 2004·Granted Jul 31, 2007·7 cites·14 claims
- 2859US2025176233A1Semiconductor deviceMEDIATEK INC·Filed 2024·Application pending·0 cites
- 2958US2024019491A1Method and apparatus for performing die-level electrical parameter extraction through using estimated mapping relationship between electrical parameters of transistor types and measurement results of logic blocksMEDIATEK INC·Filed 2023·Application pending·0 cites
- 3057US2025371234A1Central Processing Unit Turbo Yield Boosting Method and System Based on an Explainable Artificial Intelligence FrameworkMEDIATEK INC·Filed 2025·Application pending·0 cites
- 3157US2024339447A1Electrostatic discharge protection deviceMEDIATEK INC·Filed 2024·Application pending·0 cites
- 3256US9899261B2Semiconductor package structure and method for forming the sameMEDIATEK INC·Filed 2016·Granted Feb 20, 2018·0 cites·23 claims
- 3356US2025176275A1Electrostatic discharge protection deviceMEDIATEK INC·Filed 2023·Application pending·0 cites
- 3455US9786560B2Semiconductor package structure having first and second guard ring regions of different conductivity types and method for forming the sameMEDIATEK INC·Filed 2016·Granted Oct 10, 2017·0 cites·18 claims
- 3555US8836043B2Lateral bipolar junction transistorMEDIATEK INC·Filed 2014·Granted Sep 16, 2014·0 cites·5 claims
- 3652US9712130B2Passive device cell and fabrication process thereofMEDIATEK INC·Filed 2015·Granted Jul 18, 2017·0 cites·16 claims
- 3752US8188578B2Seal ring structure for integrated circuitsLEE TUNG-HSING·Filed 2008·Granted May 29, 2012·0 cites·25 claims
- 3851US11264470B2Lateral bipolar junction transistor device and method of making such a deviceGLOBALFOUNDRIES US INC·Filed 2020·Granted Mar 1, 2022·0 cites·16 claims
- 3951US9607894B2Radio-frequency device package and method for fabricating the sameMEDIATEK INC·Filed 2015·Granted Mar 28, 2017·0 cites·9 claims
- 4051US9425098B2Radio-frequency device package and method for fabricating the sameMEDIATEK INC·Filed 2015·Granted Aug 23, 2016·0 cites·12 claims
- 4150US2009294897A1Seal ring structure for integrated circuitsLEE TUNG-HSING·Filed 2008·Application pending·0 cites
- 4248US11610839B2Dummy fill structuresGLOBALFOUNDRIES US INC·Filed 2019·Granted Mar 21, 2023·0 cites·19 claims
- 4348US11289474B2Passive devices over polycrystalline semiconductor finsGLOBALFOUNDRIES US INC·Filed 2020·Granted Mar 29, 2022·0 cites·20 claims
- 4445US9859356B2Semiconductor integrated circuitMEDIATEK INC·Filed 2016·Granted Jan 2, 2018·0 cites·18 claims
- 4543US2015364549A1Semiconductor device with silicon carbide embedded dummy patternMEDIATEK INC·Filed 2014·Application pending·0 cites
- 4643US2010213507A1Lateral bipolar junction transistorKO CHING-CHUNG·Filed 2009·Application pending·0 cites
- 4742US2016027772A1Integrated capacitor in an integrated circuitMEDIATEK INC·Filed 2014·Application pending·0 cites
- 4840US8816810B2Integrated circuit transformerHUNG CHENG-CHOU·Filed 2012·Granted Aug 26, 2014·0 cites·20 claims
- 4940US7294541B2Method of fabricating gate dielectric layer and method of fabricating semiconductor deviceUNITED MICROELECTRONICS CORP·Filed 2005·Granted Nov 13, 2007·0 cites·20 claims
- 5040US2020373410A1Contact structures over an active region of a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2019·Application pending·0 cites
Showing the top 50 of 59 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →