Seal ring structure for integrated circuits

Abstract

A seal ring structure for an integrated circuit includes a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise. A P+ region is provided in a P substrate and positioned under the second portion. A shallow trench isolation (STI) structure surrounds the P+ region and laterally extends underneath a conductive rampart of the second portion.

1 . A seal ring structure for an integrated circuit, comprising:
 a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise;   a P+ region in a P substrate and positioned under the second portion; and   a shallow trench isolation (STI) structure surrounding the P+ region and laterally extending underneath a conductive rampart of the second portion.   
     
     
         2 . The seal ring structure according to  claim 1  wherein the seal ring is discontinuous, the second portion is spaced apart from the first portion. 
     
     
         3 . The seal ring structure according to  claim 1  further comprising a continuous outer seal ring outside the seal ring. 
     
     
         4 . The seal ring structure according to  claim 1  wherein a length of the second portion is equal to or greater than a span of the shielded analog and/or RF circuit block. 
     
     
         5 . The seal ring structure according to  claim 1  wherein the second portion comprises a conductive rampart that is a stack comprising a polysilicon layer, a metal layer, a contact/via layer, or a combination thereof and is manufactured together with the fabrication of the integrated circuit. 
     
     
         6 . The seal ring structure according to  claim 1  wherein no P well is formed under the P+ region. 
     
     
         7 . A seal ring structure for an integrated circuit, comprising:
 a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise;   a deep N well in a P substrate and positioned under the second portion;   a P+ region within the deep N well; and   a shallow trench isolation (STI) structure surrounding the P+ region.   
     
     
         8 . The seal ring structure according to  claim 7  wherein the seal ring is discontinuous, the second portion is spaced apart from the first portion. 
     
     
         9 . The seal ring structure according to  claim 7  further comprising a continuous outer seal ring outside the seal ring. 
     
     
         10 . The seal ring structure according to  claim 7  wherein a length of the second portion is equal to or greater than a span of the shielded analog and/or RF circuit block. 
     
     
         11 . The seal ring structure according to  claim 7  wherein the deep N well has a junction depth of about 19000-21000 angstroms. 
     
     
         12 . The seal ring structure according to  claim 7  wherein the deep N well is grounded or coupled to a supply voltage. 
     
     
         13 . The seal ring structure according to  claim 7  wherein the second portion comprises a conductive rampart that is a stack comprising a polysilicon layer, a metal layer, a contact/via layer, or a combination thereof and is manufactured together with the fabrication of the integrated circuit. 
     
     
         14 . The seal ring structure according to  claim 7  wherein no P well is formed under the P+ region.