Inventor · disambiguated record
Vencent Chang
Also filed as: CHANG VENCENT · CHANG VENCENT S
19 granted patents·5 pending applications·156 citations·filing 2001–2013
93Inventor score
Top patents by PatentIndex Score
24 records- 0189US7432042B2Immersion lithography process and mask layer structure applied in the sameUNITED MICROELECTRONICS CORP·Filed 2003·Granted Oct 7, 2008·34 cites·7 claims
- 0288US7767570B2Dummy vias for damascene processTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Aug 3, 2010·15 cites·14 claims
- 0385US6458705B1Method for forming via-first dual damascene interconnect structureUNITED MICROELECTRONICS CORP·Filed 2001·Granted Oct 1, 2002·44 cites·20 claims
- 0484US7960821B2Dummy vias for damascene processTAIWAN SEMICONDUCTOR MFG·Filed 2010·Granted Jun 14, 2011·6 cites·20 claims
- 0579US8394576B2Method for patterning a photosensitive layerLU HSIAO-TZU·Filed 2012·Granted Mar 12, 2013·2 cites·20 claims
- 0677US7648918B2Method of pattern formation in semiconductor fabricationTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Jan 19, 2010·4 cites·18 claims
- 0777US6680252B2Method for planarizing barc layer in dual damascene processUNITED MICROELECTRONICS CORP·Filed 2001·Granted Jan 20, 2004·25 cites·19 claims
- 0876US8124323B2Method for patterning a photosensitive layerLU HSIAO-TZU·Filed 2007·Granted Feb 28, 2012·4 cites·20 claims
- 0975US7531399B2Semiconductor devices and methods with bilayer dielectricsTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted May 12, 2009·5 cites·17 claims
- 1074US8119533B2Pattern formation in semiconductor fabricationLIU GEORGE·Filed 2009·Granted Feb 21, 2012·3 cites·20 claims
- 1174US7642101B2Semiconductor device having in-chip critical dimension and focus patternsTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Jan 5, 2010·4 cites·14 claims
- 1267US7387969B2Top patterned hardmask and method for patterningTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Jun 17, 2008·2 cites·14 claims
- 1362US6844143B2Sandwich photoresist structure in photolithographic processUNITED MICROELECTRONICS CORP·Filed 2002·Granted Jan 18, 2005·8 cites·7 claims
- 1459US8815496B2Method for patterning a photosensitive layerTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Aug 26, 2014·0 cites·20 claims
- 1555US8623231B2Method for etching an ultra thin filmLIU GEORGE·Filed 2008·Granted Jan 7, 2014·0 cites·17 claims
- 1653US2008153012A1Method of measuring the overlay accuracy of a multi-exposure processUNITED MICROELECTRONICS CORP·Filed 2008·Application pending·0 cites
- 1752US8384159B2Semiconductor devices and methods with bilayer dielectricsTAIWAN SEMICONDUCTOR MFG·Filed 2009·Granted Feb 26, 2013·0 cites·19 claims
- 1848US9366969B2Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabricationTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Jun 14, 2016·0 cites·20 claims
- 1947US8472005B2Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabricationLIU GEORGE·Filed 2007·Granted Jun 25, 2013·0 cites·19 claims
- 2045US9091923B2Contrast enhancing exposure system and method for use in semiconductor fabricationLIU GEORGE·Filed 2007·Granted Jul 28, 2015·0 cites·10 claims
- 2144US2008102648A1Method and System For Making Photo-Resist PatternsTAIWAN SEMICONDUCTOR MFG·Filed 2006·Application pending·0 cites
- 2242US2005244729A1Method of measuring the overlay accuracy of a multi-exposure processUNITED MICROELECTRONICS CORP·Filed 2004·Application pending·0 cites
- 2338US2004166448A1Method for shrinking the image of photoresistUNITED MICROELECTRONICS CORP·Filed 2003·Application pending·0 cites
- 2437US2004166447A1Method for shrinking pattern photoresistFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →