Inventor · disambiguated record
Vikrant Chauhan
Also filed as: CHAUHAN VIKRANT · CHAUHAN VIKRANT KUMAR
14 granted patents·2 pending applications·30 citations·filing 2012–2020
88Inventor score
Top patents by PatentIndex Score
16 records- 0184US8856715B1Capacitor designs for integrated circuits utilizing self-aligned double patterning (SADP)GLOBALFOUNDRIES INC·Filed 2013·Granted Oct 7, 2014·8 cites·20 claims
- 0283US10199270B2Multi-directional self-aligned multiple patterningGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 5, 2019·5 cites·20 claims
- 0382US10347543B2FDSOI semiconductor device with contact enhancement layer and method of manufacturingGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 9, 2019·4 cites·19 claims
- 0479US10236350B2Method, apparatus and system for a high density middle of line flowGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 19, 2019·3 cites·19 claims
- 0575US8932961B2Critical dimension and pattern recognition structures for devices manufactured using double patterning techniquesMEHTA SOHAN·Filed 2012·Granted Jan 13, 2015·5 cites·4 claims
- 0672US9465907B2Multi-polygon constraint decomposition techniques for use in double patterning applicationsGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 11, 2016·3 cites·20 claims
- 0771US9412655B1Forming merged lines in a metallization layer by replacing sacrificial lines with conductive linesGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 9, 2016·2 cites·20 claims
- 0858US11036913B2Integrated circuit methods using single-pin imaginary devicesMARVELL ASIA PTE LTD·Filed 2020·Granted Jun 15, 2021·0 cites·4 claims
- 0952US10579774B2Integrated circuit (IC) design systems and methods using single-pin imaginary devicesGLOBALFOUNDRIES INC·Filed 2018·Granted Mar 3, 2020·0 cites·10 claims
- 1052US2015050811A1Critical dimension and pattern recognition structures for devices manufactured using double patterning techniquesGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 1145US10796973B2Test structures connected with the lowest metallization levels in an interconnect structureGLOBALFOUNDRIES INC·Filed 2019·Granted Oct 6, 2020·0 cites·17 claims
- 1245US10311186B2Three-dimensional pattern risk scoringGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 4, 2019·0 cites·14 claims
- 1344US10790204B2Test structure leveraging the lowest metallization level of an interconnect structureGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 29, 2020·0 cites·18 claims
- 1439US10078107B2Wafer level electrical test for optical proximity correction and/or etch biasGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 18, 2018·0 cites·11 claims
- 1537US10147783B2On-chip capacitors with floating islandsGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 4, 2018·0 cites·16 claims
- 1634US2018040505A1Method for forming a shallow trench isolation structure using a nitride liner and a diffusionless annealGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →