Inventor · disambiguated record
Virinder Grewal
Also filed as: GREWAL VIRINDER · GREWAL VIRINDER S · GREWAL VIRINDER SINGH
18 granted patents·3 pending applications·609 citations·filing 1982–2006
96Inventor score
Top patents by PatentIndex Score
21 records- 0193US7658969B2Chemical vapor deposition chamber with dual frequency bias and method for manufacturing a photomask using the sameAPPLIED MATERIALS INC·Filed 2006·Granted Feb 9, 2010·19 cites·9 claims
- 0291US5597438AEtch chamber having three independently controlled electrodesSIEMENS AG·Filed 1995·Granted Jan 28, 1997·99 cites·20 claims
- 0389US4482209AMirror structureSIEMENS AG·Filed 1982·Granted Nov 13, 1984·71 cites·7 claims
- 0474US6300235B1Method of forming multi-level coplanar metal/insulator films using dual damascene with sacrificial flowable oxideSIEMENS AG·Filed 1997·Granted Oct 9, 2001·48 cites·23 claims
- 0574US5976986ALow pressure and low power C12 /HC1 process for sub-micron metal etchingIBM·Filed 1996·Granted Nov 2, 1999·50 cites·13 claims
- 0674US5723381AFormation of self-aligned overlapping bitline contacts with sacrificial polysilicon fill-in studSIEMENS AG·Filed 1995·Granted Mar 3, 1998·36 cites·17 claims
- 0771US4372809AMethod for manufacturing solderable, temperable, thin film tracks which do not contain precious metalSIEMENS AG·Filed 1982·Granted Feb 8, 1983·23 cites·8 claims
- 0869US4764245AMethod for generating contact holes with beveled sidewalls in intermediate oxide layersSIEMENS AG·Filed 1987·Granted Aug 16, 1988·36 cites·6 claims
- 0967US6897155B2Method for etching high-aspect-ratio featuresAPPLIED MATERIALS INC·Filed 2002·Granted May 24, 2005·11 cites·19 claims
- 1067US5874363APolycide etching with HCL and chlorineTOSHIBA KK·Filed 1996·Granted Feb 23, 1999·35 cites·10 claims
- 1167US5846884AMethods for metal etching with reduced sidewall build up during integrated circuit manufacturingSIEMENS AG·Filed 1997·Granted Dec 8, 1998·34 cites·21 claims
- 1262US5591301APlasma etching methodSIEMENS AG·Filed 1994·Granted Jan 7, 1997·33 cites·7 claims
- 1361US6008121AEtching high aspect contact holes in solid state devicesSIEMENS AG·Filed 1996·Granted Dec 28, 1999·29 cites·8 claims
- 1460US5212114AProcess for global planarizing of surfaces for integrated semiconductor circuitsSIEMENS AG·Filed 1990·Granted May 18, 1993·35 cites·11 claims
- 1558US5262002AMethod for manufacturing a trench structure in a substrateSIEMENS AG·Filed 1992·Granted Nov 16, 1993·19 cites·13 claims
- 1651US5529197APolysilicon/polycide etch process for sub-micron gate stacksSIEMENS AG·Filed 1994·Granted Jun 25, 1996·20 cites·20 claims
- 1748US2007031609A1Chemical vapor deposition chamber with dual frequency bias and method for manufacturing a photomask using the sameKUMAR AJAY·Filed 2005·Application pending·0 cites
- 1843US5926689AProcess for reducing circuit damage during PECVD in single wafer PECVD systemIBM·Filed 1995·Granted Jul 20, 1999·11 cites·3 claims
- 1937US2003222296A1Method of forming a capacitor using a high K dielectric materialAPPLIED MATERIALS INC·Filed 2002·Application pending·0 cites
- 2032US2002177323A1Gate etch process for 12 inch wafersFiled 2001·Application pending·0 cites
- 2130US6071820AMethod for patterning integrated circuit conductorsSIEMENS AG·Filed 1997·Granted Jun 6, 2000·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →