Inventor · disambiguated record
Vinod Kariat
Also filed as: KARIAT VINOD
19 granted patents·279 citations·filing 2002–2013
95Inventor score
Top patents by PatentIndex Score
19 records- 0196US7882471B1Timing and signal integrity analysis of integrated circuits with semiconductor process variationsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 1, 2011·56 cites·23 claims
- 0294US8595669B1Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2008·Granted Nov 26, 2013·39 cites·26 claims
- 0392US9129078B1Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stagesCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Sep 8, 2015·14 cites·15 claims
- 0491US8543954B1Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designsKELLER IGOR·Filed 2008·Granted Sep 24, 2013·28 cites·28 claims
- 0590US8516420B1Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source modelKARIAT VINOD·Filed 2007·Granted Aug 20, 2013·19 cites·33 claims
- 0689US8103996B2Method and apparatus for thermal analysis of through-silicon via (TSV)KARIAT VINOD·Filed 2009·Granted Jan 24, 2012·21 cites·38 claims
- 0788US8966421B1Static timing analysis methods for integrated circuit designs using a multi-CCC current source modelCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Feb 24, 2015·8 cites·8 claims
- 0887US8631369B1Methods, systems, and apparatus for timing and signal integrity analysis of integrated circuits with semiconductor process variationsKARIAT VINOD·Filed 2010·Granted Jan 14, 2014·10 cites·7 claims
- 0985US7900166B2Method to produce an electrical model of an integrated circuit substrate and related system and article of manufactureCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Mar 1, 2011·16 cites·18 claims
- 1084US8504958B2Method and apparatus for thermal analysisKARIAT VINOD·Filed 2011·Granted Aug 6, 2013·8 cites·19 claims
- 1183US8104006B2Method and apparatus for thermal analysisKARIAT VINOD·Filed 2008·Granted Jan 24, 2012·13 cites·29 claims
- 1279US8104007B2Method and apparatus for thermal analysisKARIAT VINOD·Filed 2008·Granted Jan 24, 2012·9 cites·27 claims
- 1376US8543952B2Method and apparatus for thermal analysis of through-silicon via (TSV)KARIAT VINOD·Filed 2011·Granted Sep 24, 2013·4 cites·20 claims
- 1476US8201113B2Method and apparatus for multi-die thermal analysisPRAMONO EDDY·Filed 2008·Granted Jun 12, 2012·7 cites·20 claims
- 1575US8533644B1Multi-CCC current source models and static timing analysis methods for integrated circuit designsKARIAT VINOD·Filed 2010·Granted Sep 10, 2013·3 cites·10 claims
- 1672US7877713B2Method and apparatus for substrate noise analysis using substrate tile model and tile gridCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jan 25, 2011·4 cites·18 claims
- 1772US6836873B1Static noise analysis with noise window estimation and propagationCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Dec 28, 2004·19 cites·30 claims
- 1862US8566760B2Method and apparatus for multi-die thermal analysisPRAMONO EDDY·Filed 2012·Granted Oct 22, 2013·1 cites·18 claims
- 1950US8694934B2Method and apparatus for multi-die thermal analysisPRAMONO EDDY·Filed 2012·Granted Apr 8, 2014·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →