Inventor · disambiguated record
Vladimir Bliznetsov
Also filed as: BLIZNETSOV VLADIMIR · BLIZNETSOV VLADIMIR N
7 granted patents·3 pending applications·141 citations·filing 2002–2017
86Inventor score
Files withAGENCY SCIENCE TECH & RES4UNISANTIS ELECT SINGAPORE PTE3MASUOKA FUJIO2INST OF MICROELECTRONICS1
Top patents by PatentIndex Score
10 records- 0191US6743713B2Method of forming dual damascene pattern using dual bottom anti-reflective coatings (BARC)INST OF MICROELECTRONICS·Filed 2002·Granted Jun 1, 2004·87 cites·24 claims
- 0289US9153697B2Surrounding gate transistor (SGT) structureMASUOKA FUJIO·Filed 2011·Granted Oct 6, 2015·9 cites·11 claims
- 0389US8486785B2Surround gate CMOS semiconductor deviceMASUOKA FUJIO·Filed 2011·Granted Jul 16, 2013·12 cites·10 claims
- 0477US7248773B2Method to trim and smooth high index contrast waveguide structuresAGENCY SCIENCE TECH & RES·Filed 2006·Granted Jul 24, 2007·6 cites·15 claims
- 0576US8609494B2Surround gate CMOS semiconductor deviceUNISANTIS ELECT SINGAPORE PTE·Filed 2013·Granted Dec 17, 2013·4 cites·2 claims
- 0672US6913994B2Method to form Cu/OSG dual damascene structure for high performance and reliable interconnectsAGENCY SCIENCE TECH & RES·Filed 2003·Granted Jul 5, 2005·20 cites·30 claims
- 0751US2016308013A1Semiconductor device and production methodUNISANTIS ELECT SINGAPORE PTE·Filed 2016·Application pending·0 cites
- 0849US7162133B2Method to trim and smooth high index contrast waveguide structuresAGENCY SCIENCE TECH & RES·Filed 2004·Granted Jan 9, 2007·3 cites·12 claims
- 0949US2015357428A1Surrounding gate transistor (sgt) structureUNISANTIS ELECT SINGAPORE PTE·Filed 2015·Application pending·0 cites
- 1030US2021104659A1Memory cell, memory device, and methods of forming the sameAGENCY SCIENCE TECH & RES·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →