Inventor · disambiguated record
Xi-Wei Lin
Also filed as: LIN XI · LIN XI-WEI
76 granted patents·16 pending applications·1,533 citations·filing 1997–2024
99Inventor score
Files withSYNOPSYS INC40VLSI TECHNOLOGY INC25KONINKL PHILIPS ELECTRONICS NV5MOROZ VICTOR5HON HAI PREC IND CO LTD3
Top patents by PatentIndex Score
92 records- 0197US7926018B2Method and apparatus for generating a layout for a transistorSYNOPSYS INC·Filed 2007·Granted Apr 12, 2011·108 cites·19 claims
- 0297US7895548B2Filler cells for design optimization in a place-and-route systemSYNOPSYS INC·Filed 2007·Granted Feb 22, 2011·128 cites·34 claims
- 0396US7484198B2Managing integrated circuit stress using dummy diffusion regionsSYNOPSYS INC·Filed 2006·Granted Jan 27, 2009·48 cites·8 claims
- 0495US11984384B2Power routing for 2.5D or 3D integrated circuits including a buried power rail and interposer with power delivery networkSYNOPSYS INC·Filed 2021·Granted May 14, 2024·2 cites·13 claims
- 0595US9547740B2Methods for fabricating high-density integrated circuit devicesSYNOPSYS INC·Filed 2014·Granted Jan 17, 2017·17 cites·15 claims
- 0695US7542891B2Method of correlating silicon stress to device instance parameters for circuit simulationSYNOPSYS INC·Filed 2006·Granted Jun 2, 2009·40 cites·25 claims
- 0794US8964453B2SRAM layoutsSYNOPSYS INC·Filed 2013·Granted Feb 24, 2015·16 cites·36 claims
- 0893US11742247B2Epitaxial growth of source and drain materials in a complementary field effect transistor (CFET)SYNOPSYS INC·Filed 2021·Granted Aug 29, 2023·2 cites·20 claims
- 0993US7681164B2Method and apparatus for placing an integrated circuit device within an integrated circuit layoutSYNOPSYS INC·Filed 2007·Granted Mar 16, 2010·31 cites·17 claims
- 1092US5854510ALow power programmable fuse structuresVLSI TECHNOLOGY INC·Filed 1997·Granted Dec 29, 1998·114 cites·24 claims
- 1191US7897479B2Managing integrated circuit stress using dummy diffusion regionsSYNOPSYS INC·Filed 2008·Granted Mar 1, 2011·18 cites·14 claims
- 1291US7767515B2Managing integrated circuit stress using stress adjustment trenchesSYNOPSYS INC·Filed 2006·Granted Aug 3, 2010·18 cites·19 claims
- 1391US7600207B2Stress-managed revision of integrated circuit layoutsSYNOPSYS INC·Filed 2006·Granted Oct 6, 2009·24 cites·33 claims
- 1491US5882998ALow power programmable fuse structures and methods for making the sameVLSI TECHNOLOGY INC·Filed 1998·Granted Mar 16, 1999·99 cites·14 claims
- 1589US7669161B2Minimizing effects of interconnect variations in integrated circuit designsSYNOPSYS INC·Filed 2007·Granted Feb 23, 2010·17 cites·36 claims
- 1689US5883011AMethod of removing an inorganic antireflective coating from a semiconductor substrateVLSI TECHNOLOGY INC·Filed 1997·Granted Mar 16, 1999·105 cites·21 claims
- 1787US10311200B2Pre-silicon design rule evaluationSYNOPSYS INC·Filed 2016·Granted Jun 4, 2019·7 cites·36 claims
- 1887US8086990B2Method of correlating silicon stress to device instance parameters for circuit simulationLIN XI-WEI·Filed 2009·Granted Dec 27, 2011·16 cites·14 claims
- 1985US12080608B2Self-limiting manufacturing techniques to prevent electrical shorts in a complementary field effect transistor (CFET)SYNOPSYS INC·Filed 2021·Granted Sep 3, 2024·1 cites·16 claims
- 2085US5953612ASelf-aligned silicidation technique to independently form silicides of different thickness on a semiconductor deviceVLSI TECHNOLOGY INC·Filed 1997·Granted Sep 14, 1999·63 cites·24 claims
- 2184US8504969B2Filler cells for design optimization in a place-and-route systemLIN XI-WEI·Filed 2010·Granted Aug 6, 2013·8 cites·12 claims
- 2284US7908573B2Minimizing effects of interconnect variations in integrated circuit designsSYNOPSYS INC·Filed 2009·Granted Mar 15, 2011·11 cites·28 claims
- 2383US9147027B2Chip cross-section identification and rendering during failure analysisSYNOPSYS INC·Filed 2014·Granted Sep 29, 2015·6 cites·31 claims
- 2483US6207543B1Metallization technique for gate electrodes and local interconnectsVLSI TECHNOLOGY INC·Filed 1997·Granted Mar 27, 2001·58 cites·18 claims
- 2582US8701054B2Boosting transistor performance with non-rectangular channelsMOROZ VICTOR·Filed 2011·Granted Apr 15, 2014·5 cites·40 claims
- 2681US8069430B2Stress-managed revision of integrated circuit layoutsMOROZ VICTOR·Filed 2009·Granted Nov 29, 2011·8 cites·7 claims
- 2780US9418189B2SRAM layoutsSYNOPSYS INC·Filed 2014·Granted Aug 16, 2016·4 cites·94 claims
- 2879US8686512B2Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performanceMOROZ VICTOR·Filed 2011·Granted Apr 1, 2014·4 cites·7 claims
- 2978US5834356AMethod of making high resistive structures in salicided process semiconductor devicesVLSI TECHNOLOGY INC·Filed 1997·Granted Nov 10, 1998·42 cites·21 claims
- 3077US8847324B2Increasing ION /IOFF ratio in FinFETs and nano-wiresSYNOPSYS INC·Filed 2012·Granted Sep 30, 2014·4 cites·25 claims
- 3176US6420273B1Self-aligned etch-stop layer formation for semiconductor devicesKONINKL PHILIPS ELECTRONICS NV·Filed 1999·Granted Jul 16, 2002·39 cites·21 claims
- 3276US2024395630A1Self-limiting manufacturing techniques to prevent electrical shorts in a complementary field effect transistor (cfet)SYNOPSYS INC·Filed 2024·Application pending·0 cites
- 3374US7739095B2Method for determining best and worst cases for interconnects in timing analysisSYNOPSYS INC·Filed 2007·Granted Jun 15, 2010·6 cites·27 claims
- 3473US8219961B2Method for compensation of process-induced performance variation in a MOSFET integrated circuitMOROZ VICTOR·Filed 2011·Granted Jul 10, 2012·3 cites·26 claims
- 3572US8694942B2Filler cells for design optimization in a place-and-route systemSYNOPSYS INC·Filed 2013·Granted Apr 8, 2014·2 cites·13 claims
- 3672US6143613ASelective exclusion of silicide formation to make polysilicon resistorsVLSI TECHNOLOGY INC·Filed 1997·Granted Nov 7, 2000·34 cites·24 claims
- 3772US5933739ASelf-aligned silicidation structure and method of formation thereofVLSI TECHNOLOGY INC·Filed 1997·Granted Aug 3, 1999·32 cites·11 claims
- 3871US9379018B2Increasing Ion/Ioff ratio in FinFETs and nano-wiresSYNOPSYS INC·Filed 2014·Granted Jun 28, 2016·3 cites·64 claims
- 3970US8035168B2Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performanceSYNOPSYS INC·Filed 2006·Granted Oct 11, 2011·3 cites·8 claims
- 4070US6074921ASelf-aligned processing of semiconductor device featuresVLSI TECHNOLOGY INC·Filed 1997·Granted Jun 13, 2000·37 cites·14 claims
- 4168US6093656AMethod of minimizing dishing during chemical mechanical polishing of semiconductor metals for making a semiconductor deviceVLSI TECHNOLOGY INC·Filed 1998·Granted Jul 25, 2000·35 cites·13 claims
- 4268US6084464AOn-chip decoupling capacitor system with parallel fuseVLSI TECHNOLOGY INC·Filed 1999·Granted Jul 4, 2000·26 cites·7 claims
- 4366US7949985B2Method for compensation of process-induced performance variation in a MOSFET integrated circuitSYNOPSYS INC·Filed 2007·Granted May 24, 2011·3 cites·12 claims
- 4465US8824647B2Electronic device with function of replying to message based on receiver environment and method thereofLIN XI·Filed 2011·Granted Sep 2, 2014·3 cites·18 claims
- 4565US6150266ALocal interconnect formed using silicon spacerVLSI TECHNOLOGY INC·Filed 1999·Granted Nov 21, 2000·27 cites·13 claims
- 4665US5985749AMethod of forming a via hole structure including CVD tungsten silicide barrier layerVLSI TECHNOLOGY INC·Filed 1997·Granted Nov 16, 1999·31 cites·11 claims
- 4765US5963784AMethods of determining parameters of a semiconductor device and the width of an insulative spacer of a semiconductor deviceVLSI TECHNOLOGY INC·Filed 1997·Granted Oct 5, 1999·30 cites·53 claims
- 4863US8776005B1Modeling mechanical behavior with layout-dependent material propertiesSYNOPSYS INC·Filed 2013·Granted Jul 8, 2014·2 cites·36 claims
- 4963US5880006AMethod for fabrication of a semiconductor deviceVLSI TECHNOLOGY INC·Filed 1998·Granted Mar 9, 1999·24 cites·18 claims
- 5062US6228707B1Semiconductor arrangement having capacitive structure and manufacture thereofPHILIPS SEMICONDUCTORS INC·Filed 1999·Granted May 8, 2001·22 cites·22 claims
Showing the top 50 of 92 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →