Inventor · disambiguated record
Xunyuan Zhang
Also filed as: ZHANG XUNYUAN
124 granted patents·25 pending applications·739 citations·filing 2012–2023
99Inventor score
Top patents by PatentIndex Score
149 records- 0198US9824921B1Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate capsGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 21, 2017·32 cites·10 claims
- 0297US10026687B1Metal interconnects for super (skip) via integrationGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 17, 2018·20 cites·8 claims
- 0397US9824970B1Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structuresGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 21, 2017·15 cites·13 claims
- 0497US9805972B1Skip via structuresGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 31, 2017·36 cites·20 claims
- 0597US9721889B1Middle of the line (MOL) metal contactsGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 1, 2017·21 cites·20 claims
- 0697US9412660B1Methods of forming V0 structures for semiconductor devices that includes recessing a contact structureGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 9, 2016·24 cites·14 claims
- 0797US9190486B2Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitanceGLOBALFOUNDRIES INC·Filed 2012·Granted Nov 17, 2015·35 cites·20 claims
- 0897US9190260B1Topological method to build self-aligned MTJ without a maskGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 17, 2015·39 cites·14 claims
- 0996US9941278B2Method and apparatus for placing a gate contact inside an active region of a semiconductorGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 10, 2018·13 cites·20 claims
- 1096US9530691B1Methods, apparatus and system for forming a dielectric field for dual orientation self aligned viasGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 27, 2016·15 cites·20 claims
- 1195US10211147B2Metal-insulator-metal capacitors with dielectric inner spacersGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 19, 2019·11 cites·20 claims
- 1295US9853110B2Method of forming a gate contact structure for a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2015·Granted Dec 26, 2017·13 cites·18 claims
- 1395US9589836B1Methods of forming ruthenium conductive structures in a metallization layerGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 7, 2017·16 cites·15 claims
- 1495US9159610B2Hybrid manganese and manganese nitride barriers for back-end-of-line metallization and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 13, 2015·22 cites·20 claims
- 1595US8586473B1Methods for fabricating integrated circuits with ruthenium-lined copperTANWAR KUNALJEET·Filed 2012·Granted Nov 19, 2013·45 cites·20 claims
- 1694US10199271B1Self-aligned metal wire on contact structure and method for forming sameGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 5, 2019·10 cites·8 claims
- 1794US9984919B1Inverted damascene interconnect structuresGLOBALFOUNDRIES INC·Filed 2017·Granted May 29, 2018·11 cites·17 claims
- 1894US9831174B1Devices and methods of forming low resistivity noble metal interconnectGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 28, 2017·9 cites·13 claims
- 1994US9177858B1Methods for fabricating integrated circuits including barrier layers for interconnect structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 3, 2015·32 cites·20 claims
- 2094US9018711B1Selective growth of a work-function metal in a replacement metal gate of a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Apr 28, 2015·14 cites·15 claims
- 2193US10199264B2Self aligned interconnect structuresGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 5, 2019·7 cites·18 claims
- 2293US9911604B1Sidewall spacer pattern formation methodGLOBALFOUNDRIES INC·Filed 2017·Granted Mar 6, 2018·10 cites·20 claims
- 2393US9553017B2Methods for fabricating integrated circuits including back-end-of-the-line interconnect structuresGLOBALFOUNDRIES INC·Filed 2015·Granted Jan 24, 2017·10 cites·19 claims
- 2492US11754784B2Grating couplerCISCO TECH INC·Filed 2021·Granted Sep 12, 2023·2 cites·15 claims
- 2592US10164104B2Method to form air-gap spacers and air-gap spacer-containing structuresGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 25, 2018·8 cites·11 claims
- 2692US10109490B1Cobalt interconnects formed by selective bottom-up fillGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 23, 2018·8 cites·18 claims
- 2792US10014297B1Methods of forming integrated circuit structure using extreme ultraviolet photolithography technique and related integrated circuit structureGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 3, 2018·9 cites·20 claims
- 2891US9922929B1Self aligned interconnect structuresGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 20, 2018·6 cites·19 claims
- 2991US9064948B2Methods of forming a semiconductor device with low-k spacers and the resulting deviceGLOBALFOUNDARIES INC·Filed 2012·Granted Jun 23, 2015·11 cites·14 claims
- 3090US10109526B1Etch profile control during skip via formationGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 23, 2018·9 cites·18 claims
- 3190US9040421B2Methods for fabricating integrated circuits with improved contact structuresGLOBALFOUNDRIES INC·Filed 2013·Granted May 26, 2015·8 cites·20 claims
- 3290US8691696B2Methods for forming an integrated circuit with straightened recess profileCAI XIUYU·Filed 2012·Granted Apr 8, 2014·11 cites·18 claims
- 3390US8609531B1Methods of selectively forming ruthenium liner layerGLOBAL FOUNDRIES INC·Filed 2013·Granted Dec 17, 2013·11 cites·18 claims
- 3489US9966338B1Pre-spacer self-aligned cut formationGLOBALFOUNDRIES INC·Filed 2017·Granted May 8, 2018·5 cites·18 claims
- 3589US9953834B1Method of making self-aligned continuity cuts in mandrel and non-mandrel metal linesGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 24, 2018·5 cites·10 claims
- 3689US9425280B2Semiconductor device with low-K spacersGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 23, 2016·6 cites·17 claims
- 3789US8753975B1Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 17, 2014·10 cites·21 claims
- 3889US8517769B1Methods of forming copper-based conductive structures on an integrated circuit deviceLIN SEAN X·Filed 2012·Granted Aug 27, 2013·14 cites·41 claims
- 3988US10079208B2IC structure with interface liner and methods of forming sameGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 18, 2018·5 cites·15 claims
- 4088US9190323B2Semiconductor devices with copper interconnects and methods for fabricating sameZHANG XUNYUAN·Filed 2012·Granted Nov 17, 2015·11 cites·17 claims
- 4188US9076816B2Method and device for self-aligned contact on a non-recessed metal gateGLOBALFOUNDRIES INC·Filed 2013·Granted Jul 7, 2015·9 cites·20 claims
- 4287US11036069B2Optical modulator using monocrystalline and polycrystalline siliconCISCO TECH INC·Filed 2019·Granted Jun 15, 2021·2 cites·8 claims
- 4387US9799555B1Cobalt interconnects covered by a metal capGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 24, 2017·5 cites·11 claims
- 4487US9275874B2Methods for fabricating integrated circuits using chemical mechanical planarization to recess metalGLOBALFOUNDRIES INC·Filed 2013·Granted Mar 1, 2016·7 cites·19 claims
- 4587US8907483B2Semiconductor device having a self-forming barrier layer at via bottomGLOBALFOUNDRIES INC·Filed 2012·Granted Dec 9, 2014·7 cites·19 claims
- 4687US8623758B1Subtractive metal multi-layer barrier layer for interconnect structureGLOBALFOUNDRIES INC·Filed 2012·Granted Jan 7, 2014·8 cites·20 claims
- 4786US9859120B1Method of making self-aligned continuity cuts in mandrel and non-mandrel metal linesGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 2, 2018·4 cites·10 claims
- 4886US9299745B2Integrated circuits having magnetic tunnel junctions (MTJ) and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 29, 2016·5 cites·18 claims
- 4985US10969546B2Electro-optic modulator with monocrystalline semiconductor waveguidesCISCO TECH INC·Filed 2018·Granted Apr 6, 2021·4 cites·20 claims
- 5085US10283608B2Low resistance contacts to source or drain region of transistorGLOBALFOUNDRIES INC·Filed 2017·Granted May 7, 2019·4 cites·11 claims
Showing the top 50 of 149 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →