Inventor · disambiguated record
Yeongim Park
Also filed as: PARK YEONGIM
7 granted patents·2 pending applications·55 citations·filing 2009–2012
83Inventor score
Technology areasH10W
Top patents by PatentIndex Score
9 records- 0194US8357564B2Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor dieSTATS CHIPPAC LTD·Filed 2010·Granted Jan 22, 2013·21 cites·25 claims
- 0290US9190297B2Semiconductor device and method of forming a stackable semiconductor package with vertically-oriented discrete electrical devices as interconnect structuresCHOI DAESIK·Filed 2011·Granted Nov 17, 2015·14 cites·36 claims
- 0382US9153476B2Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor dieSTATS CHIPPAC LTD·Filed 2012·Granted Oct 6, 2015·5 cites·25 claims
- 0479US8587129B2Integrated circuit packaging system with through silicon via base and method of manufacture thereofCHI HEEJO·Filed 2009·Granted Nov 19, 2013·8 cites·20 claims
- 0578US8710668B2Integrated circuit packaging system with laser hole and method of manufacture thereofLEE HYUNGMIN·Filed 2011·Granted Apr 29, 2014·7 cites·18 claims
- 0648US8426955B2Integrated circuit packaging system with a stack package and method of manufacture thereofCHI HEEJO·Filed 2009·Granted Apr 23, 2013·0 cites·18 claims
- 0745US8723309B2Integrated circuit packaging system with through silicon via and method of manufacture thereofSHIN HANGIL·Filed 2012·Granted May 13, 2014·0 cites·18 claims
- 0838US2013075923A1Integrated circuit packaging system with encapsulation and method of manufacture thereofPARK YEONGIM·Filed 2011·Application pending·0 cites
- 0933US2012326324A1Integrated circuit packaging system with package stacking and method of manufacture thereofLEE HYUNGMIN·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →