Inventor · disambiguated record
Yu-Tsung Lai
Also filed as: LAI YU-TSUNG
43 granted patents·9 pending applications·114 citations·filing 2005–2025
97Inventor score
Top patents by PatentIndex Score
52 records- 0194US9741614B1Method of preventing trench distortionUNITED MICROELECTRONICS CORP·Filed 2016·Granted Aug 22, 2017·12 cites·17 claims
- 0293US8883648B1Manufacturing method of semiconductor structureUNITED MICROELECTRONICS CORP·Filed 2013·Granted Nov 11, 2014·28 cites·20 claims
- 0389US7378343B2Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon contentUNITED MICROELECTRONICS CORP·Filed 2005·Granted May 27, 2008·20 cites·20 claims
- 0488US8993433B2Manufacturing method for forming a self aligned contactUNITED MICROELECTRONICS CORP·Filed 2013·Granted Mar 31, 2015·9 cites·13 claims
- 0587US12349367B2Semiconductor device and method for fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2023·Granted Jul 1, 2025·0 cites·7 claims
- 0687US2025301662A1Semiconductor device and method for fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2025·Application pending·0 cites
- 0786US11387408B2Magnetoresistive random access memory and method of manufacturing the sameUNITED MICROELECTRONICS CORP·Filed 2020·Granted Jul 12, 2022·1 cites·6 claims
- 0885US12133474B2Magnetoresistive random access memory and method of manufacturing the sameUNITED MICROELECTRONICS CORP·Filed 2023·Granted Oct 29, 2024·0 cites·5 claims
- 0985US10916694B2Magnetoresistive random access memory (MRAM) deviceUNITED MICROELECTRONICS CORP·Filed 2019·Granted Feb 9, 2021·2 cites·5 claims
- 1084US10903269B2Magnetic memory device and fabrication method thereofUNITED MICROELECTRONICS CORP·Filed 2019·Granted Jan 26, 2021·4 cites·20 claims
- 1184US9773860B1Capacitor and method for fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2016·Granted Sep 26, 2017·4 cites·16 claims
- 1283US12471498B2Semiconductor device and method for fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2023·Granted Nov 11, 2025·0 cites·5 claims
- 1382US10910553B1Magnetoresistive random access memory and method of manufacturing the sameUNITED MICROELECTRONICS CORP·Filed 2019·Granted Feb 2, 2021·1 cites·6 claims
- 1482US9779942B1Method of forming patterned mask layerUNITED MICROELECTRONICS CORP·Filed 2016·Granted Oct 3, 2017·3 cites·15 claims
- 1581US8298935B2Dual damascene processCHEN SHIN-CHI·Filed 2010·Granted Oct 30, 2012·5 cites·19 claims
- 1679US11812669B2Magnetoresistive random access memory and method of manufacturing the sameUNITED MICROELECTRONICS CORP·Filed 2022·Granted Nov 7, 2023·0 cites·5 claims
- 1778US7977244B2Semiconductor manufacturing processUNITED MICROELECTRONICS CORP·Filed 2006·Granted Jul 12, 2011·6 cites·12 claims
- 1877US11778922B2Semiconductor device and method for fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2021·Granted Oct 3, 2023·0 cites·13 claims
- 1977US11545522B2Semiconductor device and method for fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2021·Granted Jan 3, 2023·0 cites·8 claims
- 2076US11785785B2Semiconductor device and method for fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2021·Granted Oct 10, 2023·0 cites·8 claims
- 2175US11737370B2Magnetoresistive random access memory (MRAM) deviceUNITED MICROELECTRONICS CORP·Filed 2021·Granted Aug 22, 2023·0 cites·5 claims
- 2275US11706993B2Method of manufacturing magnetoresistive random access memory (MRAM) deviceUNITED MICROELECTRONICS CORP·Filed 2020·Granted Jul 18, 2023·0 cites·6 claims
- 2375US7767578B2Damascene interconnection structure and dual damascene process thereofUNITED MICROELECTRONICS CORP·Filed 2007·Granted Aug 3, 2010·5 cites·30 claims
- 2473US10847709B1Semiconductor device and method for fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2019·Granted Nov 24, 2020·1 cites·7 claims
- 2570US7947565B2Forming method of porous low-k layer and interconnect processUNITED MICROELECTRONICS CORP·Filed 2007·Granted May 24, 2011·4 cites·17 claims
- 2669US8350246B2Structure of porous low-k layer and interconnect structureUNITED MICROELECTRONICS CORP·Filed 2011·Granted Jan 8, 2013·2 cites·25 claims
- 2767US10636744B2Memory device including alignment mark trenchUNITED MICROELECTRONICS CORP·Filed 2018·Granted Apr 28, 2020·2 cites·20 claims
- 2866US11283007B2Semiconductor device and method for fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2020·Granted Mar 22, 2022·0 cites·11 claims
- 2965US11056536B2Semiconductor device and method for fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2019·Granted Jul 6, 2021·0 cites·1 claims
- 3063US8735295B2Method of manufacturing dual damascene structureLEE CHANG-HSIAO·Filed 2012·Granted May 27, 2014·2 cites·18 claims
- 3163US8282842B2Cleaning method following opening etchWANG CHIEH-JU·Filed 2007·Granted Oct 9, 2012·3 cites·16 claims
- 3257US11121307B2Semiconductor device and method for fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2019·Granted Sep 14, 2021·0 cites·13 claims
- 3354US10699913B2Manufacturing method for trenchUNITED MICROELECTRONICS CORP·Filed 2018·Granted Jun 30, 2020·0 cites·13 claims
- 3451US2010105205A1Cleaning solution and semicondcutor process using the sameUNITED MICROELECTRONICS CORP·Filed 2008·Application pending·0 cites
- 3550US8791013B2Pattern forming methodCHEN SHIN-CHI·Filed 2012·Granted Jul 29, 2014·0 cites·19 claims
- 3649US11271154B2Magnetic tunnel junction (MTJ) deviceUNITED MICROELECTRONICS CORP·Filed 2019·Granted Mar 8, 2022·0 cites·10 claims
- 3747US8277674B2Method of removing post-etch residuesLEE CHANG-HSIAO·Filed 2009·Granted Oct 2, 2012·0 cites·11 claims
- 3847US8080877B2Damascene interconnection structure and dual damascene process thereofHUANG CHUN-JEN·Filed 2010·Granted Dec 20, 2011·0 cites·8 claims
- 3946US10199232B2Conductor line structureCHEN SHIN CHI·Filed 2011·Granted Feb 5, 2019·0 cites·7 claims
- 4046US8137472B2Semiconductor processLEE CHANG-HSIAO·Filed 2011·Granted Mar 20, 2012·0 cites·15 claims
- 4146US2010018944A1Patterning methodUNITED MICROELECTRONICS CORP·Filed 2008·Application pending·0 cites
- 4246US2012061840A1Damascene interconnection structure and dual damascene process thereofHUANG CHUN-JEN·Filed 2011·Application pending·0 cites
- 4345US10804138B2Method for fabricating a semiconductor deviceUNITED MICROELECTRONICS CORP·Filed 2017·Granted Oct 13, 2020·0 cites·11 claims
- 4444US9230812B2Method for forming semiconductor structure having openingUNITED MICROELECTRONICS CORP·Filed 2013·Granted Jan 5, 2016·0 cites·18 claims
- 4543US2014342553A1Method for Forming Semiconductor Structure Having OpeningUNITED MICROELECTRONICS CORP·Filed 2013·Application pending·0 cites
- 4639US8828878B2Manufacturing method for dual damascene structureLIAO DUAN QUAN·Filed 2011·Granted Sep 9, 2014·0 cites·17 claims
- 4739US2011130008A1Method to control critical dimensionHSIEH MING-DA·Filed 2009·Application pending·0 cites
- 4836US2018061752A1Semiconductor device and method for fabricating the sameUNITED MICROELECTRONICS CORP·Filed 2016·Application pending·0 cites
- 4935US8592304B2Method for filling metalLEE CHANG-HSIAO·Filed 2010·Granted Nov 26, 2013·0 cites·15 claims
- 5033US2012156885A1Method and system for processing semiconductor waferLEE CHANG-HSIAO·Filed 2010·Application pending·0 cites
Showing the top 50 of 52 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Yu-Tsung Lai files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →