Inventor · disambiguated record
Yuansheng Ma
Also filed as: MA YUANSHENG
14 granted patents·3 pending applications·116 citations·filing 2007–2023
91Inventor score
Files withSIEMENS IND SOFTWARE INC4GLOBALFOUNDRIES INC3MENTOR GRAPHICS CORP3MA YUANSHENG2RASHED MAHBUB2
Top patents by PatentIndex Score
17 records- 0194US8741763B2Layout designs with via routing structuresMA YUANSHENG·Filed 2012·Granted Jun 3, 2014·38 cites·17 claims
- 0293US8581348B2Semiconductor device with transistor local interconnectsRASHED MAHBUB·Filed 2011·Granted Nov 12, 2013·20 cites·16 claims
- 0392US9836556B2Optical proximity correction for directed-self-assembly guiding patternsMENTOR GRAPHICS CORP·Filed 2016·Granted Dec 5, 2017·6 cites·16 claims
- 0492US8679911B2Cross-coupling-based design using diffusion contact structuresWANG YAN·Filed 2012·Granted Mar 25, 2014·14 cites·12 claims
- 0587US9159724B2Cross-coupling-based design using diffusion contact structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 13, 2015·8 cites·20 claims
- 0687US9006100B2Middle-of-the-line constructs using diffusion contact structuresRASHED MAHBUB·Filed 2012·Granted Apr 14, 2015·9 cites·14 claims
- 0785US9330228B2Generating guiding patterns for directed self-assemblyMENTOR GRAPHICS CORP·Filed 2015·Granted May 3, 2016·4 cites·20 claims
- 0879US7861195B2Process for design of semiconductor circuitsADVANCED MIRCO DEVICES INC·Filed 2008·Granted Dec 28, 2010·10 cites·7 claims
- 0978US9142513B2Middle-of-the-line constructs using diffusion contact structuresGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 22, 2015·3 cites·20 claims
- 1068US12411405B2Optical proximity correction based on combining inverse lithography technology with pattern classificationSIEMENS IND SOFTWARE INC·Filed 2022·Granted Sep 9, 2025·0 cites·19 claims
- 1164US8598633B2Semiconductor device having contact layer providing electrical connectionsTARABBIA MARC·Filed 2012·Granted Dec 3, 2013·3 cites·19 claims
- 1259US8367430B2Shape characterization with elliptic fourier descriptor for contact or any closed structures on the chipGLOBALFOUNDRIES INC·Filed 2009·Granted Feb 5, 2013·1 cites·17 claims
- 1352US10311165B2Guiding patterns optimization for directed self-assemblyMENTOR GRAPHICS CORP·Filed 2016·Granted Jun 4, 2019·0 cites·20 claims
- 1452US2024386177A1Circuit design and manufacturing hotspot root cause extractionSIEMENS IND SOFTWARE INC·Filed 2023·Application pending·0 cites
- 1552US2024427967A1Monotonic Machine Learning-Based Sub-Resolution Assist FeaturesSIEMENS IND SOFTWARE INC·Filed 2023·Application pending·0 cites
- 1647US2025036849A1Realistic test circuit generation through random circuit layer blocksSIEMENS IND SOFTWARE INC·Filed 2023·Application pending·0 cites
- 1744US8067252B2Method for determining low-noise power spectral density for characterizing line edge roughness in semiconductor wafer processingMA YUANSHENG·Filed 2007·Granted Nov 29, 2011·0 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →