Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink—harmonic wrinkle reduction

Abstract

A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

The invention claimed is: 
     
       1. An accumulated charge control N-type MOSFET (ACC N-MOSFET) adapted to control charge accumulated in a body of the ACC N-MOSFET, comprising:
 a) a gate, drain, source and a gate oxide layer positioned between the gate and the body, wherein the ACC N-MOSFET is biased to operate in an accumulated charge regime when the ACC N-MOSFET is operated in a non-conducting or near non-conducting state; 
 b) a first accumulated charge sink (ACS) region positioned proximate a first distal end of the body, wherein the first ACS region is coupled to the body, and wherein, when the ACC N-MOSFET is operated in the accumulated charge regime, a first ACS bias voltage is applied to the first ACS region to control or to remove accumulated charge from the ACC N-MOSFET body via the first ACS region; and 
 c) a second accumulated charge sink (ACS) positioned proximate a second distal end of the body, wherein the second ACS region is coupled to the body and wherein, when the ACC N-MOSFET is operated in the accumulated charge regime, a second ACS bias voltage is applied to the second ACS region to control or to remove accumulated charge from the ACC N-MOSFET body via the second ACS region, 
 
       wherein the first ACS bias voltage and the second ACS bias voltage are negative with respect to ground, drain and source. 
     
     
       2. The ACC N-MOSFET of  claim 1 , wherein the ACC N-MOSFET is fabricated in a silicon-on-insulator technology, wherein a silicon layer of a silicon-on-insulator substrate has a thickness between approximately 100 angstroms to approximately 2000 angstroms. 
     
     
       3. The ACC N-MOSFET of  claim 1 , wherein the ACC N-MOSFET is fabricated in a silicon-on-insulator technology, wherein the drain and the source extend through a silicon layer of a silicon-on-insulator substrate and the drain and the source are proximate to an insulating layer below the silicon layer of the silicon-on-insulator substrate. 
     
     
       4. The ACC N-MOSFET of  claim 1 , wherein the ACC N-MOSFET is fabricated in a silicon-on-insulator technology, wherein a silicon film of a silicon-on-insulator substrate is a thin film. 
     
     
       5. The ACC N-MOSFET of  claim 1 , wherein the first ACS region and the second ACS region are electrically equivalent. 
     
     
       6. The ACC N-MOSFET of  claim 5 , wherein the first ACS region and the second ACS region are positioned symmetrically with respect to a center of the body. 
     
     
       7. The ACC N-MOSFET of  claim 6 , further comprising a first electrical contact region and a second electrical contact region, wherein the first electrical contact region is coupled to the first ACS and the second electrical contact region is coupled to the second ACS. 
     
     
       8. The ACC N-MOSFET of  claim 7 , wherein the first electrical contact region and the second electrical contact region are electrically equivalent. 
     
     
       9. The ACC N-MOSFET of  claim 8 , wherein the first electrical contact region and the second electrical contact region are positioned symmetrically along a line defined by middle of the body between the source and the drain. 
     
     
       10. The ACC N-MOSFET of  claim 9 , wherein the first electrical contact region and the second electrical contact region have equal dimensions. 
     
     
       11. The ACC N-MOSFET of  claim 10 , wherein the first ACS bias voltage and the second ACS bias voltage are applied via the first electrical contact region and the second electrical contact region, respectively. 
     
     
       12. The ACC N-MOSFET of  claim 11 , wherein the first electrical contact region is coupled to the second electrical contact region through a path having a low impedance. 
     
     
       13. The ACC N-MOSFET of  claim 12 , wherein the first ACS couples to the body at a first ACS impedance and the second ACS couples to the body at a second impedance and wherein the first impedance is equal to the second impedance. 
     
     
       14. The ACC N-MOSFET of  claim 12 , wherein the first electrical contact region and the second electrical contact region are coupled using one of a metal layer and conductive semiconductor layer. 
     
     
       15. The ACC N-MOSFET of  claim 14 , wherein the conductive semiconductor layer comprises P+ doping. 
     
     
       16. The ACC N-MOSFET of  claim 15 , wherein the first ACS and the second ACS are coupled to the gate. 
     
     
       17. The ACC N-MOSFET of  claim 16 , wherein the source and the drain comprise N+ doped regions, the body, the first ACS and the second ACS comprise P− doped regions and the first electrical contact region and the second electrical contact region comprise P+ doped region. 
     
     
       18. The ACC N-MOSFET of  claim 17 , wherein the first ACS couples to the body at a first ACS impedance and the second ACS couples to the body at a second impedance and wherein the first impedance is equal to the second impedance. 
     
     
       19. An accumulated charge control N-type MOSFET (ACC N-MOSFET) adapted to control charge accumulated in a body of the N-MOSFET, comprising:
 a) a gate, drain, source, and a gate oxide layer positioned between the gate and the body, wherein the ACC N-MOSFET is biased to operate in an accumulated charge regime when the ACC N-MOSFET is operated in a non-conducting or near non-conducting state; 
 b) a plurality of accumulated charge sinks positioned proximate portions of the body, wherein each accumulated charge sink is coupled to the body, and wherein the ACC N-MOSFET is biased to operate in an accumulated charge regime, and wherein accumulated charge sink bias voltages are applied to the plurality of accumulated charge sinks to control or to remove accumulated charge from the ACC N-MOSFET body via the plurality of accumulated charge sinks; 
 wherein the accumulated charge sink bias voltages are negative with respect to ground, the source and the drain. 
 
     
     
       20. The ACC N-MOSFET of  claim 19 , wherein the ACC N-MOSFET is fabricated in a silicon-on-insulator technology, wherein a silicon layer of a silicon-on-insulator substrate has a thickness between approximately 100 angstroms to approximately 2000 angstroms. 
     
     
       21. The ACC N-MOSFET of  claim 19 , wherein the ACC N-MOSFET is fabricated in a silicon-on-insulator technology, wherein the drain and the source extend through a silicon layer of a silicon-on-insulator substrate and the drain and the source are proximate to an insulating layer below the silicon layer of the silicon-on-insulator substrate. 
     
     
       22. The ACC N-MOSFET of  claim 19 , wherein the ACC N-MOSFET is fabricated in a silicon-on-insulator technology, wherein a silicon film of a silicon-on-insulator substrate is a thin film. 
     
     
       23. The ACC N-MOSFET of  claim 19 , further comprising a plurality of electrical contact regions positioned proximate to corresponding accumulated charge sinks, wherein the plurality of electrical contact regions are coupled to the corresponding accumulated charge sinks. 
     
     
       24. The ACC N-MOSFET of  claim 23 , wherein the plurality of electrical contact regions are coupled to one another via one or more paths, the one or more paths having one or more path impedances. 
     
     
       25. The ACC N-MOSFET of  claim 24 , wherein each of the accumulated charge sinks is coupled to the body at one or more accumulated charge sink impedances and the one or more path impedances are less than the one or more accumulated charge sink impedances. 
     
     
       26. The ACC N-MOSFET of  claim 25 , wherein the plurality of accumulated charge sinks are biased through the corresponding plurality of electrical contact regions. 
     
     
       27. The ACC N-MOSFET of  claim 26 , wherein each accumulated charge sink is coextensive with its corresponding contact region. 
     
     
       28. The ACC N-MOSFET of  claim 27 , wherein each electrical contact region is coupled independently to the gate. 
     
     
       29. The ACC N-MOSFET of  claim 28 , further comprising a gate terminal coupled to the gate, a drain terminal coupled to the drain, a source terminal coupled to the source, and one or more ACS terminals coupled to one or more of the electrical contact regions. 
     
     
       30. The ACC N-MOSFET of  claim 23 , wherein the drain, the gate, and the plurality of accumulated charge sinks are disposed symmetrically along a line defined by the middle of the body between the source and the drain.