US10424508B2ActiveUtilityA1

Interconnection structure having a via structure and fabrication thereof

49
Assignee: DELTA ELECTRONICS INCPriority: Nov 13, 2012Filed: Jun 24, 2015Granted: Sep 24, 2019
Est. expiryNov 13, 2032(~6.4 yrs left)· nominal 20-yr term from priority
H10P 34/42H10P 14/47H10W 90/724H10W 90/722H10W 72/9226H10W 72/07254H10W 72/07236H10W 72/01923H10W 72/952H10W 72/944H10W 72/942H10W 72/934H10W 72/923H10W 72/922H10W 72/881H10W 72/879H10W 72/871H10W 72/252H10W 72/247H10W 72/244H10W 72/241H10W 72/072H10W 72/29H10W 70/65H10W 99/00H10W 90/811H10W 90/00H10W 70/481H10W 20/0698H10W 20/077H10W 20/057H10W 20/20H10W 20/0261H10W 20/0249H10D 64/254H10D 62/8503H10W 20/023H01L 2224/16148H01L 2224/0401H01L 25/18H01L 2224/16146H01L 21/76895H01L 25/074H01L 2224/73255H01L 2924/00012H01L 2224/0332H01L 21/76898H01L 2224/16147H01L 2224/131H01L 24/91H01L 2224/13147H01L 2924/13064H01L 2224/05147H01L 23/49575H01L 24/05H01L 2224/05548H01L 23/49562H01L 25/50H01L 2924/00014H01L 2224/81193H01L 2224/0557H01L 2224/02372H01L 23/481H01L 2224/05557H01L 2924/12042H01L 2224/16238H01L 2224/81815H01L 2924/014H01L 2224/17181H01L 24/13H01L 2224/13024H01L 21/76834H01L 2224/05599H01L 2224/73257H01L 24/16H01L 21/2885H01L 2224/05552H01L 21/268H01L 2224/73221H01L 2224/05009H01L 2924/00H01L 2224/06181H01L 21/76879H01L 24/03H01L 24/81H10D 30/475
49
PatentIndex Score
0
Cited by
31
References
12
Claims

Abstract

A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method of forming an interconnection structure comprising:
 providing a substrate having a first side and a second side opposite to the first side; 
 forming at least one electric device on the substrate, wherein the at least one electric device comprises a plurality of metal electrodes; 
 forming a via hole through one of the plurality of the metal electrodes of the electric device and the substrate, wherein the via hole has a first opening neighboring the first side and a second opening neighboring the second side; 
 forming a first pad covering the first opening and directly on the at least one electric device, wherein a portion of the at least one electric device is between the first pad and the substrate; and 
 forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure comprises a conductive material and is adjoined to the first pad, and the via structure exceeds the second opening. 
 
     
     
       2. The method of forming an interconnection structure as claimed in  claim 1 , further comprising:
 forming a photosensitive layer on the substrate covering the at least one electric device prior to forming the via hole. 
 
     
     
       3. The method of forming an interconnection structure as claimed in  claim 1 , further comprising forming an insulating layer surrounding a sidewall of the via hole prior to forming the via structure. 
     
     
       4. The method of forming an interconnection structure as claimed in  claim 1 , wherein forming the first pad comprises performing a first metal screen printing process to form the first pad covering the first opening. 
     
     
       5. The method of forming an interconnection structure as claimed in  claim 1 , further comprising forming a second pad covering the via hole subsequent to forming the via structure. 
     
     
       6. The method of forming an interconnection structure as claimed in  claim 1 , wherein forming the via hole through the substrate comprises drilling the via hole through the substrate with a laser beam. 
     
     
       7. The method of forming an interconnection structure as claimed in  claim 1 , wherein forming the via structure is performed by electric plating using the first pad as a seed layer. 
     
     
       8. The method for forming an interconnection structure as claimed in  claim 1 , wherein the metal electrode of the electric device being through by the via hole is a drain electrode. 
     
     
       9. A method for forming an interconnection structure, comprising:
 providing a substrate having a first side a second side opposite to the first side; 
 forming at least one electric device on the substrate, wherein the at least one electric device comprises a plurality of metal electrodes; 
 forming a via hole through one of the plurality of the metal electrodes of the electric device and the substrate, wherein the via hole has a first opening neighboring the first side and a second opening neighboring the second side; and 
 performing a screen printing process on the first side to fill a conductive material into the via hole so as to form a via structure in the via hole and a first pad disposed on the first side and directly on the at least one electric device, adjoined to the via structure, and the via structure exceeds the second opening, wherein a portion of the at least one electric device is between the first pad and the substrate. 
 
     
     
       10. The method for forming an interconnection structure as claimed in  claim 9 , further comprising:
 forming a photosensitive layer on the substrate covering the at least one electric device prior to forming the via hole. 
 
     
     
       11. The method for forming an interconnection structure as claimed in  claim 9 , further comprising forming an insulating layer surrounding a sidewall of the via hole prior to forming the via structure. 
     
     
       12. The method for forming an interconnection structure as claimed in  claim 9 , wherein the metal electrode of the electric device being through by the via hole is a drain electrode.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.