Systems and methods for a semiconductor structure having multiple semiconductor-device layers

Abstract

A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included. The bottom surface of the SOI substrate is bonded to the patterned top surface of the first semiconductor device layer via the bonding surface.

What is claimed is: 
     
       1. A device comprising:
 a first semiconductor device layer including a first semiconductor device; 
 a second semiconductor device layer including a plurality of fins, a plurality of gates disposed over the plurality of fins and gate spacers on sidewalls of the plurality of gates, wherein a first subset of the gate spacers extend to contact a first oxide layer and a second subset of the gate spacers extend to contact at least one fin from the plurality of fins; and 
 the first oxide layer disposed between the first semiconductor device layer and the second semiconductor device layer, wherein the first oxide layer electrically insulates the plurality of fins from the first semiconductor device. 
 
     
     
       2. The device of  claim 1 , wherein the second semiconductor device layer further includes a second semiconductor device performing a different function than the first semiconductor device. 
     
     
       3. The device of  claim 1 , further comprising a second oxide layer disposed over the first semiconductor device layer; and
 a metal layer disposed over the first semiconductor device layer, wherein the metal layer and the second oxide layer are disposed between the first oxide layer and the first semiconductor device layer. 
 
     
     
       4. The device of  claim 3 , wherein the second oxide layer and the metal layer both physically contact the first oxide layer. 
     
     
       5. The device of  claim 3 , further comprising a third oxide layer disposed within the first semiconductor device layer, and
 wherein the second oxide layer interfaces with the third oxide layer. 
 
     
     
       6. The device of  claim 1 , wherein at least one of the plurality of fins extends to the first oxide layer. 
     
     
       7. The device of  claim 1 , further comprising a third semiconductor device layer disposed over the second semiconductor device layer, the third semiconductor device layer including a memory device, and
 a fourth semiconductor device layer disposed over the third semiconductor device layer, the fourth semiconductor device layer including an RF/IO circuit. 
 
     
     
       8. A device comprising:
 a first semiconductor device layer including a first semiconductor device, wherein the first semiconductor device layer includes a top surface having a dielectric portion and a conductive portion; 
 a dielectric layer disposed directly on the first semiconductor device layer such that dielectric layer physically contacts the dielectric portion and the conductive portion of the top surface of the first semiconductor device layer; and 
 a second semiconductor device layer disposed over the dielectric layer, the second semiconductor device layer including a fin structure, a gate disposed over the fin structure and a gate spacer disposed along a sidewall of the gate such that the gate spacer extends to the dielectric layer, wherein the dielectric layer electrically insulates the fin structure from the first semiconductor device. 
 
     
     
       9. The device of  claim 8 , wherein the dielectric layer includes an oxide material. 
     
     
       10. The device of  claim 8 , wherein the dielectric portion includes an oxide material and the conductive portion includes a metal material. 
     
     
       11. The device of  claim 8 , wherein the first semiconductor device layer further includes another dielectric layer embedded within the first semiconductor device layer, and
 wherein the dielectric portion physically contacts the another dielectric layer. 
 
     
     
       12. The device of  claim 11 , wherein the first semiconductor device layer further includes a p-well and n-well, and
 wherein the another dielectric layer separated the p-well form the n-well. 
 
     
     
       13. The device of  claim 8 , wherein the fin structure physically contacts the dielectric layer. 
     
     
       14. The device of  claim 8 , further comprising a third semiconductor device layer disposed over the second semiconductor device layer, the third semiconductor device layer including a second semiconductor device performing a different function than the first semiconductor device, and
 a fourth semiconductor device layer disposed over the third semiconductor device layer, the fourth semiconductor device layer including a third semiconductor device performing a different function than the second semiconductor device. 
 
     
     
       15. The device of  claim 14 , wherein the first semiconductor device performs a function selected from a group consisting of an ESD protection function, a logic function, a memory function, an I/O function, an analog function, a passive device function, and a BJT device function, and
 wherein the second semiconductor device performs a memory function, and 
 wherein the third semiconductor device performs an RF/IO function. 
 
     
     
       16. A method comprising:
 bonding a first semiconductor device layer having a first semiconductor device to a dielectric layer of a second substrate, the second substrate including a channel material layer disposed on the dielectric layer; and 
 after bonding the first semiconductor device layer to the dielectric layer of the second substrate, forming a second semiconductor device layer on the channel material layer by patterning the channel material layer to form a fin structure on the dielectric layer and forming a gate structure on the fin structure, the second semiconductor device layer including a second semiconductor device that is different from the first semiconductor device. 
 
     
     
       17. The method of  claim 16 , wherein the dielectric layer includes an oxide material and the channel material layer includes a semiconductor material. 
     
     
       18. The method of  claim 16 , wherein the first semiconductor device layer includes a top surface having a dielectric portion and a conductive portion, and
 wherein bonding the first semiconductor device layer to the dielectric layer includes bonding the dielectric layer directly to the dielectric portion and the conductive portion of the top surface of the first semiconductor device layer. 
 
     
     
       19. The method of  claim 16 , wherein after the forming of the second semiconductor device layer on the channel material layer by patterning the channel material layer to form the fin structure on the dielectric layer, the fin structure extends from the dielectric layer. 
     
     
       20. The method of  claim 16 , further comprising forming a sidewall spacer along a sidewall of the gate structure and along a sidewall of the fin structure such that that the sidewall spacer extends to the dielectric layer.