Etching process control in forming MIM capacitor

Abstract

A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

What is claimed is: 
     
       1. A method comprising:
 forming a capacitor comprising: 
 depositing a bottom electrode layer; 
 depositing a capacitor insulator layer over the bottom electrode layer; 
 depositing a top electrode layer over the capacitor insulator layer; 
 depositing a first dielectric layer over the top electrode layer; 
 etching the first dielectric layer using a first etching gas until the top electrode layer is exposed, wherein the first dielectric layer is etched using a first etching mask; 
 etching the top electrode layer using the first etching mask to form a top electrode; 
 despositing a second dielectric layer over the top electrode; and 
 etching the second dielectric layer, the capacitor insulator layer and the bottom electrode layer using a same second etching mask to form a capacitor insulator and a bottom electrode, respectively; and 
 forming a top contact penetrating through the first dielectric layer to contact the top electrode. 
 
     
     
       2. The method of  claim 1 , wherein the etching the first dielectric layer and the etching the top electrode layer are performed using different etching gases. 
     
     
       3. The method of  claim 1 , wherein in the etching the first dielectric layer, the first dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0. 
     
     
       4. The method of  claim 1 , wherein the etching the top electrode layer results in a remaining portion of the top electrode layer to be left as the top electrode, and the top electrode has a footing profile, with lower portions of the top electrode being increasingly wider than respective upper portions of the top electrode. 
     
     
       5. The method of  claim 1 , wherein the etching the first dielectric layer comprises applying a bias power lower than about 130 Watts. 
     
     
       6. The method of  claim 1 , wherein the first dielectric layer is etched using substantially pure CF4. 
     
     
       7. The method of  claim 6 , wherein the top electrode layer is etched using an etching gas comprising CHF3 and chlorine (Cl2). 
     
     
       8. A method comprising:
 depositing a bottom electrode layer on a wafer; 
 depositing a capacitor insulator layer over the bottom electrode layer; 
 depositing a top electrode layer over the capacitor insulator layer; 
 depositing a first dielectric layer over the top electrode layer; 
 etching the first dielectric layer using a first etching gas, wherein the first etching gas comprises CF4, and is substantially free from additional carbon-and-fluorine-containing gases; 
 etching the top electrode layer using a second etching gas to form a top electrode; 
 forming a second dielectric layer on a top surface of the first dielectric layer and sidewalls of the top electrode; and 
 etching the second dielectric layer, the capacitor insulator layer, and the bottom electrode layer using a same etching mask. 
 
     
     
       9. The method of  claim 8 , wherein the first etching gas is different from the second etching gas. 
     
     
       10. The method of  claim 9 , wherein the first dielectric layer and the top electrode layer are etched using a same etching mask. 
     
     
       11. The method of  claim 8 , wherein the second etching gas comprises fluorine, and is substantially free from CF4. 
     
     
       12. The method of  claim 8 , wherein the first dielectric layer has a first etching rate in response to the first etching gas, and the top electrode layer has a second etching rate in response to the first etching gas, and a ratio of the first etching rate to the second etching rate is higher than about 5.0. 
     
     
       13. The method of  claim 8 , wherein the top electrode has a footing profile. 
     
     
       14. The method of  claim 8  further comprising:
 forming a plurality of sample wafers having top electrode layers and dielectric layers identical to the top electrode layer and the dielectric layer in the wafer, respectively; and 
 adjusting etching gases and etching process conditions for etching the dielectric layer in the plurality of sample wafers to find a etching gas and an etching process condition that results in an etching selectivity to be higher than about 5.0. 
 
     
     
       15. The method of  claim 8 , wherein the etching the first dielectric layer is performed by applying a bias power lower than about 130 Watts. 
     
     
       16. A method comprising:
 depositing a bottom electrode layer on a wafer; 
 depositing a capacitor insulator layer over the bottom electrode layer; 
 depositing a top electrode layer over the capacitor insulator layer; 
 depositing a first dielectric layer over the top electrode layer; 
 etching the first dielectric layer until the top electrode layer is exposed; 
 etching the top electrode layer to form a top electrode, wherein the top electrode has a footing profile, with lower portions of the top electrode being increasingly wider than respective upper portions of the top electrode; 
 forming a second dielectric layer covering the top electrode and a remaining portion of the first dielectric layer; and 
 patterning the second dielectric layer, the capacitor insulator layer, and the bottom electrode layer to form a capacitor, wherein remaining portions of the second dielectric layer, the capacitor insulator layer, and the bottom electrode layer extend beyond edges of the remaining portion of the first dielectric layer. 
 
     
     
       17. The method of  claim 16 , wherein the etching the first dielectric layer is performed using a first etching gas comprising substantially pure CF4, and the top electrode layer is etched using a second etching gas comprising fluorine and substantially free from CF4. 
     
     
       18. The method of  claim 17 , wherein during the etching the first dielectric layer, the first dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0. 
     
     
       19. The method of  claim 16 , wherein the first dielectric layer is etched using a first etching gas, and the top electrode layer is etched using a second etching gas, wherein the first etching gas comprises CF4 and is free from CHF3, and the second etching gas comprises CHF3 and is substantially free from CF4. 
     
     
       20. The method of  claim 19 , wherein the first etching gas comprises substantially pure CF4.